CD2481 Datasheet, PDF (214/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
Figure 29. DMA Write Cycle Timing
CLK
BUSCLK
t₂₄
t₂₅
AS*
t₃₃
t₃₄
DS*
t₂₃
A[0–7]
t₃₁
t₃₂
A/D[0–15]
DTACK*
BERR*
t₃₆
t_S
t₃₅
t_H
BERR* Timing:
t_S = setup time to CLK rising edge = 10 ns
t_H = hold time after CLK rising edge = 20 ns
214
Datasheet