CD2481 Datasheet, PDF (6/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
10.0
11.0
12.0
Index
9.4.2 Special Transmit Command Register (STCR) ..................................... 150
9.4.3 Channel Status Register (CSR) ........................................................... 153
9.4.4 Modem Signal Value Registers (MSVR) .............................................. 158
9.5 Interrupt Registers............................................................................................. 159
9.5.1 General Interrupt Registers .................................................................. 159
9.5.2 Receive Interrupt Registers.................................................................. 163
9.5.3 Transmit Interrupt Registers................................................................. 175
9.5.4 Modem Interrupt Registers................................................................... 179
9.6 DMA Registers .................................................................................................. 182
9.6.1 DMA Mode Register (DMR) ................................................................. 182
9.6.2 Bus Error Retry Count (BERCNT)........................................................ 182
9.6.3 DMA Buffer Status (DMABSTS)........................................................... 183
9.6.4 DMA Receive Registers ....................................................................... 184
9.6.5 DMA Transmit Registers ...................................................................... 189
9.7 Timer Registers................................................................................................. 197
9.7.1 Timer Period Register (TPR)................................................................ 197
9.7.2 Receive Time-Out Period Register (RTPR) – Async Modes Only ....... 197
9.7.3 General Timer 1 (GT1) – Sync Modes Only......................................... 198
9.7.4 General Timer 2 (GT2) – Sync Modes Only......................................... 199
9.7.5 Transmit Timer Register (TTR) – Async Modes Only .......................... 200
Electrical Specifications...................................................................................... 201
10.1 Absolute lectri Maximum Ratings (Revision B at 35 MHz) .............................. 201
10.2 DC Electrical Characteristics (Revision B at 35 MHz) ..................................... 201
10.3 AC Electrical Characteristics (Revision B at 35 MHz) ..................................... 202
10.4 Absolute Maximum Ratings (Revisions B and D at 60 MHz) .......................... 203
10.5 DC Electrical Characteristics (Revisions B and D at 60 MHz) ........................ 204
10.6 AC Electrical Characteristics (Revisions B and D at 60 MHz) ........................ 205
Package Specifications ....................................................................................... 215
Ordering Information Example ......................................................................... 216
....................................................................................................................................... 217
Figures
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Functional Block Diagram ................................................................................... 11
Host Read Cycle ................................................................................................. 38
Host Write Cycle ................................................................................................. 39
Interrupt Acknowledge Cycle .............................................................................. 41
Bus Acquisition Cycle.......................................................................................... 47
Data Transfer Timing .......................................................................................... 47
Transmitter A and B Buffers................................................................................ 50
Receiver A and B Buffers.................................................................................... 53
DMA Transmit Buffer Selection........................................................................... 57
Bit Rate Generator/DPLL .................................................................................... 62
Data Encoding..................................................................................................... 66
Transmit Data With External Clock In ................................................................. 66
Transmit Data With External Clock Out .............................................................. 66
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Datasheet