CD2481 Datasheet, PDF (76/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
7.1.3
If the transmitter is idling in mark, frame transmission is started when data is made available to the
transmitter, either via the TDR (Transmit Data register) or a DMA buffer. First the programmable
number of pad characters are transmitted, then the programmable number of flag characters. Data
characters are then be transmitted and a CRC value accumulated using each data character.
When end-of-frame status is passed to the CD2481 via the TEOIR or the ABTBSTS/BTBSTS, and
the remaining data is transmitted, the FCS (if enabled) and a closing flag will be appended to the
frame. If a new frame is available immediately, the correct number of opening flags will be
transmitted and data transmission started. If data is not available, the line will be returned to its idle
condition.
If data underrun occurs, the CD2481 does not append an FCS, but aborts the transmission by
sending eight continuous 1’s, and then reverts to the idle condition. An underrun interrupt is
generated, and, if interrupt transfer is being used, the CPU should provide an EOF response in
TEOIR. If DMA Transfer mode is being used, the CD2481 discards DMA buffers until an EOF
buffer is found; transmission then resumes from the next buffer. This ensures correct operation
when a multiple buffer frame underruns.
When programmed in NRZI mode and idle in mark is selected, after the closing flag and the first
eight ones are transmitted, the transmit data line is sampled to determine if it is a logic high or low.
If it is low, an extra zero is transmitted to force the line to be a logic high.
When Idle in Flag mode is selected, the send pad and opening number of flags have no
significance; transmission is started when data is first made available in the FIFO. If no data
underrun occurs, the frame is terminated normally with an FCS, and then continuous flags are
generated. If an underrun does occur, then no FCS is appended, eight ones are transmitted to abort
the frame and then continuous flags and an underrun interrupt are generated.
HDLC Receive Mode
Once enabled, the receiver enters Flag Hunt mode. When the first flag is detected, the next non-
flag/abort character is treated as the start of frame. If address recognition is not enabled, frame
reception then continues; if address recognition is enabled, the incoming data is compared with the
receive address registers, RFAR[1:4]. Two modes of address recognition are available:
1. The first byte of the address field only (four possible matches available against RFAR[1:4]).
2. The first and second byte the address field (two possible matches available against
RFAR[1:2], RFAR[3:4]).
For the purposes of address matching, the HDLC Address Extension bit is not interpreted by the
CD2481. The address matching occurs on either the complete first byte, or complete first and
second byte of the frame. If no address match is recognized, Flag Hunt mode is once again entered,
thereby discarding the current frame. If a match is found, normal frame reception continues. When
the closing flag of the frame is detected, the data remaining in the FIFO is passed to the CPU, either
through DMA transfers or good data interrupts, and then an EOF (End-of-Frame) interrupt is
generated. The FCS can be either validated or ignored. If the CD2481 does not check the FCS, it
will be passed onto the host. A validated FCS can be either discarded or passed onto the host for
diagnostic purposes.
The next non-flag/abort character will restart the process. The current state of the receive process is
visible to the CPU via the CSR register, which indicates whether data, flag or mark are currently
being received. To support the Data Phase of an X.21 connection, a Clear Detect feature can be
enabled via COR1. When enabled, the receive data and CTS* pin are monitored for the Clear
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Datasheet