CD2481 Datasheet, PDF (174/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
REOIR – Async-HDLC / PPP / SLIP / MNP4 Modes
Register Name: REOIR
Register Description: Receive End of Interrupt Register
Default Value: x’00
Access: Byte Write Only
Bit 7
Bit 6
Bit 5
Bit 4
TermBuff
DiscExc
SetTm2
SetTm1
Bit 3
NoTrans
Intel Hex Address: x’87
Motorola Hex Address: x’84
Bit 2
0
Bit 1
0
Bit 0
0
The CD2481 interprets values written to this register at the completion of all receive interrupts.
Bit 7
Terminate current DMA buffer
If this bit is set, the current receive buffer is terminated and data transfer is switched
to the other buffer. This bit should only be set in response to an async exception
interrupt. If the buffer is terminated in response to an exception character (that is,
parity error) interrupt and the discard exception character bit is not set, the exception
character is written at the start of the next buffer.
Before writing the terminate buffer command to REOIR, a new buffer descriptor can
be written to the current buffer.
Bit 6
Discard exception character (DMA mode only)
When this bit is set in response to an async exception interrupt, the exception char-
acter is not transferred to memory.
Bit 5
Set general timer 2 in Synchronous modes
0 = do not set general timer
1 = load the value, to general timer 2, provided in RISRl.
Bit 4
Set general timer 1 in Synchronous modes
0 = do not set general timer 1
1 = load the value, to the high byte of general timer 1, provided in RISRl.
At the end of an interrupt service routine, the user can set a timer by setting a timer
value in the Receive Interrupt Status register. When the timer reaches ‘0’, the
CD2481 generates a modem/timer group interrupt to the host.
Bit 3
No transfer of data
This bit must be set by the host, if no data is transferred from the receive FIFO during
a receive interrupt.
Bits 2:0
Reserved - must be zero.
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Datasheet