CD2481 Datasheet, PDF (177/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
Bit 4
Transmit underrun error (HDLC only), otherwise zero (Async, PPP, SLIP, and
MNP4).
Bit 3
BA/BB – Applicable buffer for the register interrupt
0 = Transmit Buffer A
1 = Transmit Buffer B
Bit 2
Reserved; returns ‘0’ when read.
Bit 1
TxEmpty – Transmitter empty
All characters have been completely transmitted, and the serial output is idle.
Bit 0
TxDat – The number of characters in the FIFO is below the threshold.
Note: During an interrupt service routine, the host can use this register to provide a timer value as
detailed in the Receive End of Interrupt register. The host can only load one of the two timers in the
interrupt service routine.
9.5.3.4
Transmit FIFO Transfer Count (TFTC)
Register Name: TFTC
Register Description: Transmit FIFO Transfer Count Register
Default Value: x’00
Access: Byte Read Only
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
0
0
TxCt4
TxCt3
Intel Hex Address: x’83
Motorola Hex Address: x’80
Bit 2
TxCt2
Bit 1
TxCt1
Bit 0
TxCt0
9.5.3.5
Bits 7:5
Bits 4:0
Reserved - must be zero.
Transmit data count
If the Transmit channel is interrupt driven, a non-zero value is a request for data.
These bits give the number of spaces available in the transmit FIFO.
Transmit Data Register (TDR)
Register Name: TDR
Register Description: Transmit Data Register
Default Value: x’00
Access: Byte Write Only
Bit 7
Bit 6
Bit 5
D7
D6
D5
Bit 4
D4
Bit 3
D3
Intel Hex Address: x’F8
Motorola Hex Address: x’F8
Bit 2
D2
Bit 1
D1
Bit 0
D0
This register accesses the transmit data FIFO of a channel, interrupting for transmit data transfer.
This register address is used for all channels to transfer transmit FIFO data to the host, if
programmed in Interrupt Transfer mode. Data must be written as bytes, and follows the rules listed
Datasheet
177