CD2481 Datasheet, PDF (119/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
If TxIBE is set, then transmission is stopped after the receipt of an XOFF character
(cntl-S or hex 13). Immediately after receiving an XOFF, any character in the Trans-
mit Shift register or Holding Register is transmitted, and character transmission is
halted. Thus, no more than two characters are sent after receiving an XOFF.
Depending on the IXM bit, either the receipt of an XON (cntl-Q or hex 11) character
or any character (IXM = 1) restarts the transmission. A transmit enable command by
the CCR also restarts transmission.
Bit 5
Embedded transmitter command enable (Async)
If set, the embedded special transmitter command functions are enabled. The null
(all zeroes) character is used as the ESCape character. The following functions are
supported:
00H 00H – Send one 00H character as normal data
00H 81H – Send break
Enter line break condition for at least 1 character time. (If the insert delay special
character sequence immediately follows the send break sequence, the duration of the
break transmission is extended by the amount of the programmed delay.)
00H 82H XXH – Insert delay
Insert a delay of ‘XX’ (interpreted as an unsigned binary number) times the pro-
grammed timer ‘tick’ set by the Prescaler Period registers. (A zero delay count
results in no delay.)
00H 83H – Stop break
Exit line break condition and resume normal character transmission.
Bit 4
Reserved – must be zero.
Bit 3
RLM – Remote loop back
RLM = 1 enables Remote Loopback mode.
RLM = 0 disables Remote Loopback mode.
Bit 2
RtsAO – RTS automatic output enable
If RtsAO = 1, the RTS* output pin remains enabled during DMA or character bursts
from the transmit FIFO. If the CTS* input pin goes high, then RTS* goes high and
transmission is stopped after the current burst is completed.
Bit 1
CtsAE – CTS automatic enable
When clear, the transmitter output enable is independent of the CTS* input pin.
When set, the CTS* input pin is evaluated prior to the transmission of each character.
If CTS* is asserted low, that character is transmitted completely. If CTS* is high,
that character transmission is held until CTS* goes low.
Bit 0
DsrAE – DSR automatic enable
When clear, the receiver input enable is independent of the DSR* input pin.
When set, the DSR* input pin is evaluated at the end of each received character. If
DSR* is asserted low, the receiver input is enabled for the next character. If DSR*
is high, the receiver is disabled until DSR* goes low.
Datasheet
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