CD2481 Datasheet, PDF (148/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
9.4
9.4.1
Channel Command and Status Registers
Channel Command Register (CCR)
There are two CCR command sets. Mode 1 (if bit 7 is ‘0’) commands affect basic channel control.
In Mode 2 (if bit 7 is ‘1’), additional commands that control timer functions are available.
CCR - Mode 1
Register Name: CCR
Register Description: Channel Command Register, Mode 1
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
0
ClrCh
InitCh
RstAll
Bit 3
EnTx
Intel Hex Address: x’10
Motorola Hex Address: x’13
Bit 2
DisTx
Bit 1
EnRx
Bit 0
DisRx
The various command and control bits in this register perform largely independent functions. The
host can assert multiple command bits to achieve the desired effect. The CD2481 clears the register
to zero after it accepts and acts on a host command. The host must verify that the contents of this
register are zero prior to issuing a new command. If the RESET ALL command is issued, all other
commands are ignored. All other combinations are legal, and the order of processing is as follows:
1. Clear channel
2. Initialize channel
3. Enable receive
4. Disable receive
5. Enable transmit
6. Disable transmit
Note: Processing CCR commands is a low-priority task for the internal firmware, since they seldom
occur. The user must take care when waiting for command completions at critical times, that is,
during interrupt service routines.
Channel Control Commands (Bit 7 = 0)
Bit 7
Must be zero.
Bit 6
Clear channel command
When this command is issued, the CD2481 clears the data FIFOs and current trans-
mit and receive status of the channel in the CSR. If the channel is currently transmit-
ting a frame in synchronous protocol, the host should issue the transmit abort, special
transmit command, before issuing a clear command. The channel parameters are not
affected by a channel clear command. The clear channel command causes both
receive and transmit FIFOs to be cleared, the transmitter and receiver to be disabled
and all DMA Status registers (DMABSTS, A/BRBSTS and A/BTBSTS) to be
cleared.
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Datasheet