CD2481 Datasheet, PDF (47/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
During each DMA read and write cycle, the least-significant eight memory address
bits, MA[0–7] come from A[0–7].
Figure 6 on page 47 is an example of one DMA access after bus is acquired.
Figure 5. Bus Acquisition Cycle
BR*
BGIN*
BGACK*
(Another component owns the
bus and gives it up here.)
The CD2481 owns the bus at this point.
Figure 6. Data Transfer Timing
ADLD*
AEN*
DATDIR*
AS*
High for MEM read
Low for MEM write
R/W*
DS*
High for MEM read
Low for MEM write
DTACK*
5.4.3
Bus Error Handling
When a bus error is detected during a DMA sequence, the CD2481 terminates the current bus cycle
and relinquishes the bus. Any data transfer in the bus ownership cycle is ignored, and the original
conditions are restored. A subsequent retry attempt would start again from these original
conditions.
Datasheet
47