CD2481 Datasheet, PDF (206/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
Symbol
Parameter (Sheet 2 of 2)
MIN
t₄₄
R/W* setup to CLK high
5
t₄₅
CLK high to data valid
t₄₆
Data setup time to CLK high
5
t₄₇
Data hold time after CLK high
12
t₄₈
Address setup time to CLK high
5
t₄₉
Address hold time after CLK high
10
t₅₀
CLK high to DTACK* low (read cycle)
t₅₁
CLK high to DTACK* low (write cycle)
t₅₂
(CS* and DS*) low to DATEN*/DATDIR* low
t₅₃
DS* high to DATEN*/DATDIR* tristate
t₅₄
DS* high to data bus tristate
t₅₅
DS* high to DTACK* high-impedance
Interrupt Acknowledge
t₆₁
CLK high to IACKIN*, DS* setup
17
t₆₃
CLK high to data valid
t₆₄
Address setup to IACKIN* low
0
t₆₅
Address hold after IACKIN* high
0
t₆₆
CLK high to DTACK* low
t₆₇
(IACKIN* and DS*) low and BUSCLK high to
DATEN* and DATDIR* low
1.This timing assumes the following conditions: BGACK* high, DTACK* high, DS* high, and BUSCLK high.
MAX
25
17
17
25
25
17
17
25
20
40
Figure 21. CLK / BUSCLK / RESET* Timing Relationship
CLK
BUSCLK
t_PERIOD
t_LOW
t₁
t₂
t_HIGH
RESET*
During RESET* active period, BUSCLK is held low. BUSCLK will transition high and begin running at one/half
CLK frequency on the first rising edge of CLK after RESET* release.
NOTE: BUSCLK does not free-run during microcode download.
206
Datasheet