CD2481 Datasheet, PDF (127/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
Bit 6
Bit 5
Bit 4
Bits 3:0
Steady state detect enable
When set, this bit enables the checking of special receive conditions relevant to
X.21. The conditions are:
1. All ‘0’s
2. All ‘1’s
3. Alternating ‘0’s and ‘1’s.
4. Change in the condition of the CTS* pin (CTS* is used as the ‘I’ lead for DTE or
‘C’ lead for DCE).
To be detected as a special condition, a change must be present for at least 16 bit
times. When detected, a receive exception interrupt is generated with the relevant
status set in the RISR. After detection of the special condition, no further data is
passed to the host until different data is received.
In certain phases of X.21 call setup, there is no character synchronization. When a
data change occurs in a non-character synchronous phase, a partial character can be
detected before the steady state is detected or character sync is achieved. In these
conditions, the partial character is passed to the host as normal data.
Strip SYN
When this bit is set, SYN characters are treated as special receive conditions; when
two SYN characters are received, a special character interrupt is generated (see
RISR), and following SYN characters are stripped from the incoming data stream.
If this bit is not set, the SYN characters are treated as normal data and passed to the
host in Good Data interrupts; they are still used to obtain character synchronization
with the data.
Special character detect enable
SCDE is only available when SSDE mode (see above) is enabled. If enabled, the
characters programmed in SCHR[1–3] are treated as the steady state conditions in
the SSDE mode. They are validated for two character times, a special character inter-
rupt is generated and subsequent repetitions of the same data pattern are filtered from
the data stream.
Reserved – must be zero; will read back as zero.
COR3 – Async-HDLC/PPP Mode
Register Name: COR3
Register Description: Channel Option Register 3
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Stop2
0
RxChk
TxGen
Bit 3
npad3
Bit 7
Stop2
0 = 1 Stop bit
1 = 2 Stop bit
Bit 6
Reserved – must be zero.
Intel Hex Address: x’15
Motorola Hex Address: x’16
Bit 2
npad2
Bit 1
npad1
Bit 0
npad0
Datasheet
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