CD2481 Datasheet, PDF (93/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
7.6.3
Frame = SYN SYN STX ENQ FF FF
Reported as:
receive CRC error
receive abort
STX and ENQ are passed to host as data.
CRC Calculation in Bisync Mode
When in Bisync mode, there are several conditions under which the CD2481 varies the way it
computes the FCS (frame check sequence) or BCC/CRC. The decision about which data is
included in the current frame depends on how the previous frame ended and the transparency in the
middle of a frame.
The following tables show the point in the current frame where the FCS computation begins, based
on how the previous frame ended. From the start of a frame, when the previous frame ended in
DLE-ITB, the following data streams have CRC computed as follows:
SYN
SYN
SYN
SYN
SYN
SYN
Data
Data
STX
Data
SOH
Data
CRC Begins
From the start of a frame, when the previous frame did not end in DLE-ITB, the following four
data streams have CRC computed as follows:
SYN
SYN
SYN
SYN
DLE
DLE
STX
SOH
Data
Data
CRC Begins
SYN
SYN
SOH
Data
CRC Begins
Transition from non-transparent to transparent frame:
SYN SYN SOH Data Data DLE STX Data
CRC
Within a non-transparent frame:
Datasheet
93