CD2481 Datasheet, PDF (66/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
When using an n-times external clock, the highest possible clock frequency and largest divisor
combination is recommended. The frequency of an external clock should be less than the system
CLK input divided by 16, (that is, for 33-MHz operation, the data clock should be less than 2
MHz). Note that R/TBPR is an 8-bit register; therefore the largest divisor value is 255.
Use the following equation to compute the divisor value:
Bit rate divisor = ^{F----r--e---q--u---e---n---c---y-D---o--e-f-s---ie-r--xe---td-e---rb--n-i--at---lr--a-c--tl--eo---c---k----s---o---u--r---c--e-} – 1
Figure 11. Data Encoding
DATA CLOCK
NRZ
NRZI
MANCHESTER
Figure 12. Transmit Data With External Clock In
TxCin
NRZ TxData
NOTE: When using external receive clock in the Receive mode, data is sampled on the low-to-high going edge
of RXCin.
Figure 13. Transmit Data With External Clock Out
TxCout
NRZ TxData
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Datasheet