CD2481 Datasheet, PDF (194/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
9.6.5.11
Bit 0
Ownership of the transfer buffer (set by the host CPU and cleared by the CD2481)
0 = buffer not ready to be used by the CD2481
1 = buffer is ready for the CD2481 to transmit
A Transmit Buffer Status (ATBSTS) –Async-HDLC/PPP Mode
Register Name: ATBSTS
Register Description: Transmit Buffer ‘A’ Status Register
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Berr
EOF
EOB
0
Bit 3
0
Intel Hex Address: x’5C
Motorola Hex Address: x’5F
Bit 2
map32
Bit 1
INTR
Bit 0
2481own
9.6.5.12 B Transmit Buffer Status (BTBSTS) –Async-HDLC/PPP Mode
Register Name: BTBSTS
Register Description: Transmit Buffer ‘B’ Status Register
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Berr
EOF
EOB
0
Bit 3
0
Intel Hex Address: x’5D
Motorola Hex Address: x’5E
Bit 2
map32
Bit 1
INTR
Bit 0
2481own
Bit 7
Bit 6
Bit 5
Bits 4:3
Bit 2
Bit 1
Bit 0
Berr – Bus error (set by the CD2481, and cleared by the host)
0 = No bus error
1 = Bus error was detected on the last transfer
EOF – End of frame (set and cleared by the host)
0 = This buffer is not the last in frame/block.
1 = This buffer is the last in frame/block.
EOB – The end of a transmit buffer (set by the CD2481, and cleared by the host).
The end of a host supplied transmit buffer has been reached.
Reserved – must be zero.
map32 – Map all transmit characters from 00–1F (set and cleared by the host)
0 = Use the normal TXACCM map.
1 = Map all characters in the range from 00–1F.
INTR – Interrupt
0 = No interrupt required after the buffer is transmitted.
1 = Interrupt required after the buffer is transmitted.
2481own – Ownership of the transmit buffer (set by the host and cleared by the
CD2481)
194
Datasheet