CD2481 Datasheet, PDF (145/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
9.3
9.3.1
9.3.1.1
Bit Rate and Clock Option Registers
Receive Baud Rate Generator Registers
Receive Baud Rate Period Register (RBPR)
Register Name: RBPR
Register Description: Receive Bit-Rate Period Register
Default Value: x’81
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Receive Bit Rate Period (Divisor)
Intel Hex Address: x’C9
Motorola Hex Address: x’CB
Bit 1
Bit 0
9.3.1.2
This register contains the preload value for the receive baud rate counter. When using an internal
clock option or an n-times external clock, the preload value in conjunction with the receiver clock
source chosen, determines the receive baud rate. If a 1× external clock is used, a value of 01h must
be loaded in the RBPR.
Receive Clock Option Register (RCOR)
Register Name: RCOR
Register Description: Receive Clock Option Register
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
TLVal
0
DpllEn
Dpllmd1
Bit 3
Dpllmd0
Intel Hex Address: x’CA
Motorola Hex Address: x’C8
Bit 2
ClkSel2
Bit 1
ClkSel1
Bit 0
ClkSel0
This register is used to select the DPLL mode, and the desired clock source for the receive baud
rate generator.
Bit 7
TLVal – Transmit line value
This bit reflects the logical value of the transmit data pin. It is a read-only bit; writing
to this bit has no effect.
Bit 6
Reserved – must be zero.
Bit 5
DPLL enable
1 = DPLL is enabled
0 = DPLL is disabled
Bits 4:3
DPLL mode selects the type of data encoding used.
Datasheet
145