CD2481 Datasheet, PDF (150/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
9.4.2
Bit 5
Bit 4
Bit 3
Bits 2:0
Clear timer 2
General timer 2 is cleared.
Clear receiver command
This command only affects the receiver. It resets all receiver functions like a combi-
nation of clear channel and initialize channel commands. ClrRx clears the receive
FIFO and clears receive status in the CSR, except for the RxEn bit. ClrRx clears
receive DMA buffer status in ARBSTS, BRBSTS, and Receive Status bits in
DMABSTS. Clearing the 2481OWN bits in both the Receive Buffer Status registers
means that DMA buffers have to be returned to the CD2481 before receive transfers
begin again.
For Synchronous modes, this command puts the receiver back into Syn/Flag Hunt
mode.
Clear Transmitter Command
This command only affects the transmitter; it is only available on Revision C and
later devices and only effective in asynchronous protocols. It resets all transmitter
functions like a combination of clear channel and initialize channel commands.
ClrTx clears the transmit FIFO and clears transmit status in the CSR, except for the
TxEn bit.
ClrTx clears transmit DMA buffer status in ATBSTS, BTBSTS, and Transmit Status
bits in DMABSTS. Clearing the CD2481 own bits in both the Transmit Buffer Status
registers means that DMA buffers have to be returned to the CD2481 before transmit
transfers begin again.
Reserved – must be zero.
Special Transmit Command Register (STCR)
STCR – Async and HDLC Modes
Register Name: STCR
Register Description: Special Transmit Command Register
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
0
AbortTx
AppdCmp
0
Bit 3
SndSpc
Intel Hex Address: x’11
Motorola Hex Address: x’12
Bit 2
SSPC2
Bit 1
SSPC1
Bit 0
SSPC0
The CD2481 clears the register to zero when it accepts a host CPU command.
Bit 7
Reserved – must be zero.
Bit 6
Abort transmission (HDLC)
Terminates the frame currently in transmission with an abort sequence. In DMA
mode, all data up to the next EOF is discarded.
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Datasheet