CD2481 Datasheet, PDF (37/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
5.0
Functional Description
5.1
5.1.1
Host Interface
The CD2481 is a synchronous device with an asynchronous bus interface. A stable input clock is
required on the CLK pin — nominally 60 MHz. CLK is divided by two internally, and the resulting
clock controls internal device timing and is output on the BUSCLK pin. The baud-rate generators
and timers are also related to CLK. The “AC Electrical Characteristics (Revision B at 35 MHz)”
section in Chapter 10.0 shows that many input signal setup and output signal transitions are related
to the edges of the CLK and BUSCLK signals. It is possible, however, to use the CD2481 in a
purely asynchronous bus environment.
The CD2481 can act as either bus master, during DMA transfers, or as a bus slave device during
normal host read and write transfers. Both byte and word transfers are supported in each of the Bus
Slave and DMA Bus Master modes. Figure 2 and Figure 3 show the signals involved in these
transfers.
Host Read and Write Cycles
The host read and write cycles begin with the activation of the CS* (chip select) and DS* (data
strobe) signals. The DATADIR* (data direction) and DATEN* (data enable) signals are used to
control external data buffers. The falling edge of the DTACK* (data transfer acknowledge) signal
indicates that the transfer is complete. DTACK* is released when DS* is deasserted. CS* should
also be deasserted at that time. The AS* (address strobe) is not used during slave cycles; it is an
output during DMA transfers.
Note that the following open-drain and tristate outputs should have pull-up resistors attached:
AEN*, AS*, DATADIR*, DATEN*, and DTACK*.
Datasheet
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