CD2481 Datasheet, PDF (12/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
1.2
CD2XXX Device Family Compatibility
Features
CD2481
CD2401
CD2431
CD2231
Number of serial channels
Interrupt on-chip DMA mechanism
FIFO depth (per channel and per direction)
Data size (bits)
Async
HDLC/SDLC
X.21, Bisync
Async-HDLC, PPP (point-to-point protocol)
Programmable sync
Serial data rate (kbps)
Number of modem leads
(per channel, including RxD and TxD)
On-chip timers
UNIX^ character processing
Special character Tx and recognition
Package
Pin compatibility
4
√¹
16
5-8
Downloaded²
Downloaded
Downloaded
Downloaded
Downloaded
230.4³
10
√
Downloaded
Downloaded
100-pin MQFP
CD24X1
4
√
16
5-8
√
√
√
n/a
n/a
134.4⁴
10
√
√
√
100-pin MQFP
CD24X1
4
√
16
5-8
√
√
n/a
√
n/a
134.4⁵
2
√
16
5-8
√
√
n/a
√
n/a
256/230.4⁶
10
10
√
√
√
100-pin MQFP
CD24X1
√
√
√
100-pin MQFP
CD24X1⁷
1.√ indicates identical operation and register setting.
2.Device microcode is not user-programmable; standard microcode is supplied by Intel.
3.Clock frequency of 60 MHz is required for 230.4 kbps. Applies to Revision B or later CD2481 devices.
4.Clock frequency of 35 MHz is required for 134.4 kbps (CD2401/CD2431); 256 kbps (sync)/230.4 kbps (async) (CD2231).
5.Clock frequency of 35 MHz is required for 134.4 kbps (CD2401/CD2431); 256 kbps (sync)/230.4 kbps (async) (CD2231).
6.Clock frequency of 35 MHz is required for 134.4 kbps (CD2401/CD2431); 256 kbps (sync)/230.4 kbps (async) (CD2231).
7.Compatible with all pins, except those supporting channels 2 and 3 on other family members. These pins are ‘no connects’ on
the CD2231 or must be pulled up to V_CC through a 4.7-kΩ resistor (see the CD2481 datasheet).
12
Datasheet