80KSBR200 Datasheet, PDF (95/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Case Scenario Packet Header Register
Name: CS0_PKT_HEADER
Address: 0x18400
Advanced Datasheet*
Bit
Field Name
Type
Reset
Value
Comment
1:0
PRIORITY
3:2
TT
RW
2b0
RW
2b0
sRIO Priority Packet
Transaction Type, 00 = 8 bit, 01 = 16 bit
7:4
FTYPE
RW
4h0
15:8 TARGETADDR
RW
4h0
23:16 TARGETADDR16 RW
8h0
sRIO Transaction Format Type
Destination ID for the transmission
Extension for 16 bit if TT = 01; see note 1
27:24
31:28
TTYPE
-
RW
4h0
0
Transaction Type (sub group of FTYPE)
Reserved
Note:
1:0)
3:2)
7:4)
15:8)
Table 64 Case Scenario Packet Header Register
PRIORITY - The priority for the sRIO packet header. CR is set to zero and ignored as part of the priority.
Default priority should be 00h, low priority.
TT - The sRIO transaction type. If set to 00h, the transaction is 8 bits, if set to 01h, the transaction is 16
bits. Other TT values are invalid.
FTYPE - Defined in the sRIO specification, part 1, section 4.1. The only FTYPEs supported are types 5
(WRITE) and 6 (SWRITE).
TARGET ADDRESS - The destination ID for the packet to be sent. This byte will be included in all
packets using this case scenario.
23:16)
27:24)
SIZE:
TARGET ADDRESS, x16 - The MSB of the address if the sRIO transaction is 16 bits. If TT = 00, the
target address MSBs are used.
TTYPE - The sub transaction to the FTYPE defined in the same location as FTYPE. If FTYPE is 5 the
only TTYPEs supported are NWRITE and NWRITE_R.
The size is set by the hardware and should not be part of the case scenario. See sRIO spec., section
4.1.2.
Case Scenario Start Address Register
The starting address for memory writes when performing SWRITE and NWRITE operations with this case scenario.
The address contained in the packet will increment appropriately starting from this location. Upon a wrap or reset, the
address will return to this value.
Name: CS0_STRT_ADDR
Address: 0x18404
Bit
30:0
Field Name
STRT_ADDR
31
-
Type
Reset
Value
Comment
RW
31h0
Start Address:
Starting memory address for sRIO
0
Reserved
Table 65 Case Scenario Start Address Register
Case Scenario Next Address Register
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.