80KSBR200 Datasheet, PDF (38/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
– All PLLs will be reset.
– Any existing state machines will be initialized to a known state.
– Any changes are immediate, except JTAG and I²C will perform the change at the designated command
◆ _{Load Configuration - Identical to "Partial Reset" except ports and PLLs are not reset.}
6.3.1 Programming
◆ _{Configuration Register Reset (registers without shadows) - These resets may be performed anytime on the fly}
and they affect only the designated register. They are performed by loading the individual register with a new
value. (Example of the registers affected include the destination IDs).
– sRIO maintenance packet. The registers may not be programmed through JTAG, or I²C.
– Shadow registers and configuration registers with shadows are not affected.
– Memory is not affected
– Flag registers may be individually cleared using this method. Mask registers are part of the flag register
and will be affected along with any writing to the flag registers for clearing.
– Designated error counters and status registers will be cleared (not set to a programmed value).
– PLLs are not affected
– Any existing state machines are not affected, except possibly as a result of the register changing.
– Any changes are immediate
◆ _{Shadow Register Programming - These resets may be performed anytime on the fly and they affect only the}
designated shadow register. They are performed by loading the individual register with a new value.
– Programming may be done through sRIO maintenance packets, JTAG or I²C.
– Only shadow registers are affected.
– Memory is not affected
– Flag and Flag Mask registers are not affected.
– Error counters and status registers are not affected.
– PLLs are not affected
– No existing state machines are affected.
– There is no immediate effect on any configuration register from programming a shadow register. To load
the results of the programming into the designated configuration registers, a "Load Configuration" reset
must subsequently be performed.
◆ _{Flag Register Reset - These resets may be performed anytime on the fly and they affect only the designated}
register.
– Performed with sRIO maintenance packets.
– Flag registers are cleared by writing to them. Writing the Wr32 bit within the register designates whether
the write to a flag register is intended to alter the entire register, including destination IDs, or simply clear
flags. Flags may be cleared by writing a "1" to them. Any flag that is written with a "0" will remain
unchanged.
– Some flag registers contain real time values, indicated by "RT" in the flag register section. These values
cannot be cleared except by affecting the source of the flag. A new doorbell or interrupt will not be gener-
ated if the RT flag is active.
– Error counters and status registers may be associated with flag registers and will be cleared if written to.
– JTAG and I²C may read the registers, but cannot clear the flag registers, except through a load configu-
ration type reset.
– Any changes are immediate
6.3.2 Clearing Flags
Flags are cleared by the various "resets" associated with the SerB. The methods of clearing flags are described in
section 6.3, of this datasheet. In summary, any flag may be cleared by Master Reset, a Load Configuration, or by writing to
the flag register. Any mask register may be programmed by writing to it, but it won't be affected by clearing a flag register.
38 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.