80KSBR200 Datasheet, PDF (13/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
2.0 Application
Advanced Datasheet*
2.1 PPS Data Storage
The SerB’s primary application is for a Basestations using the IDT’s Pre-Processing Switch (PPS). The SerB will be a
storage device, holding large amounts of data passed to it by the PPS and with all of its internal memory allocated to
queue 0. In this application, the S-Port on the SerB will connect to one of the 4x ports of the PPS. The PPS will pass
approximately 10ms of data to the SerB at which time the SerB will start to pass it back to the PPS as a multicast. It is
expected that the data flow will remain constant with 10ms (or other designated quantity) worth of data always in storage.
The Basestation uses the data for decryption purposes.
The following are items of note concerning the PPS application:
◆ _{The SerB has the ability to act as a simple master.}
– The SerB's application with the PPS will be to broadcast data. It must be a master to perform a broadcast,
even if the data is requested.
– The SerB has the ability to initiate writes. Mainly to prevent overflow and to perform broadcasts when
waterlevel is reached (timed event). This avoids requiring the DSP to increase congestion by requesting
data and controlling the SerB.
◆ _{The SerB will typically perform SWRITEs.}
– The target address(s) generated by the SerB is programmable.
– The packets are stored in the format they come in and are rebroadcast with simple changes to the headers
◆ _{The DSPs have the ability to read the SerB registers through the PPS.}
– The DSP may send a maintenance read/write packets to the SerB requesting register information.
High
Speed
Serial
Lines
sRIO
High
Speed
Serial
Lines
Queue 0
Data
Data
Address
CNTL
Figure 2 PPS Data Storage
2.2 Compatible External Memories
The P-Port, as a FIFO controller shall connect to an external memory device. There are two designated memory
devices, which may be connected to the SerB. These are:
◆ _{QDRII-B4 SRAM with 36-bit bus in 36M size}
◆ _{QDRII-B4 SRAM with 36-bit bus in 72M size}
Only one memory may be connected to the P-Port at a time. Initial release of the SerB will only support 72M
density and support of other devices listed above to follow with subsequent release. Expansion is available only
through increased memory size.
2.2.1 Memory Default Configurations:
The memory default configuration on power up or hard reset is as follows:
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.