80KSBR200 Datasheet, PDF (137/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
15.4.1 Boundary Scan Registers
The 80KSBR200 boundary scan chain is 140 bits long. The five JTAG pins do not have scan elements associated with
them. Full boundary scan details can be found in the associated BSDL file which may be found on our web site
(www.IDT.com). The boundary scan chain is connected between TDI and TDO when the EXTEST or SAMPLE/PRELOAD
instructions are selected. Once EXTEST is selected and the TAP controller passes through the UPDATE-IR state, what-
ever value that is currently held in the boundary scan register’s output latches is immediately transferred to the corre-
sponding outputs or output enables.
Therefore, the SAMPLE/PRELOAD instruction must first be used to load suitable values into the boundary scan cells,
so that inappropriate values are not driven out onto the system pins. All of the boundary scan cells feature a negative edge
latch, which guarantees that clock skew cannot cause incorrect data to be latched into a cell. The input cells are sample-
only cells.
The simplified logic configuration is shown in the figure below.
Input
To core logic
Pin
From previous cell
DQ
To next cell
shift_dr
clock_dr
Figure 43 Diagram of Observe-only Input Cell
The simplified logic configuration of the output cells is shown in the figure below.
Data from Core
EXTEST
To Next Cell
To Output Pad
Data from Previous Cell
shift_dr
clock_dr
D Q ^DQ
update_dr
Figure 44 Diagram of Output Cell
137 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
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