80KSBR200 Datasheet, PDF (77/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
Bit
Field Name
Reset
Value
Comment
11:4
RE_XMT_MASK
0x00
Re-transmit Suppression Mask:
Suppress packet re-transmission on CRC error.
SerB does not support this feature and these bits are set to zero.
16:12 -
0
17
ENUM_BOUN
1b0
Reserved.
Enumeration Boundary:
An enumeration boundary aware system enumeration algorithm
shall honor this flag. The algorithm, on either the ingress or the
egress port, shall not enumerate past a port with this bit set. This
provides for software enforced enumeration domains within the RIO
fabric.
18
FLO_CTRL_PART 1b0
Flow Control Participant, enable flow control transactions:
1b0 - Do not route or issue flow control transactions to this port
1b1 - Route or issue flow control transactions to this port.
(RIO spec. Part 9, sec. 4.3)
19
MULTI_PART
1b0
20
ERR_CHK_DIS
1b0
21
IN_PORT_EN
1b0
22
OUT_PORT_EN
1b0
Multicast-event Participant:
This bit is hard-wired to 0.
Error Checking Disable, this bit disables all RIO transmission error
checking:
1b0 - error checking and recovery is enabled
1b1 - error checking and recovery is disabled
Input Port Enable, input port receive enable:
0b0 - port is stopped and only enabled to route or respond to I/O log-
ical MAINTENANCE packets.
0b1 - port is enabled to respond to any packet.
Output Port Enable, output port transmit enable:
1b0 - port is stopped and not enabled to issue any packets except to
route or respond to I/O Logical Maintenance packets.
1b1 - port is enabled to issue any packets.
23
PORT_DIS
1b0
26:24 PORT_OVER
3b000
29:27 INIT_PORT_WDTH HW
Port Disable:
1b0 - Port receiver/drivers are enabled
1b1 - Port receivers/drivers are disabled and are unable to receive/
transmit any packets or control symbols
Port Width Override, soft port configuration to override the hardware
size:
3b000 No override
3b001 Reserved
3b010 Force single lane, lane 0
3b011 Force single lane, lane 2
3b100 - 3b111 Reserved
The change of this field during normal mode may cause re-initializa-
tion.
Initialized Port Width, width of the ports after initialized (read-only):
3b000 Single-lane port, lane 0
3b001 Single-lane port, lane 2
3b010 Four-lane port
3b011 - 3b111 Reserved.
31:30 PORT_WIDTH
HW
Port Width, hardware width of the port (read-only):
2b00 Single-lane port
2b01 Four-lane port
2b10 - 2b11 Reserved.
Note:
1.
Table 34 Port 0 Control CSR
The above register is described in the RIO Specification Part 6, sec. 6.6.2.9
77 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.