80KSBR200 Datasheet, PDF (93/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
Note:
1.
2.
3.
The watermark is the trigger point at which the flag will be set. As a master that will always transmit new data
as soon as it has arrived and been accepted, the watermark should be set to zero.
D-Word or Packet count indicates whether the watermark and waterlevel are in terms of packet count or in D-
Word count.
Flush or Single Packet determines what happens when data is sent out of the queue.
a. On flush, all data in the queue is transmitted, except for new data that arrives during the flush.
b. On Single Packet, only enough data is sent to lower the waterlevel below the watermark. Presumably, in
most situations, this will be a single packet or D-Word.
c. It should be noted that the Flush or Single Packet works with the Master/Slave selection in the Serial Port
Configuration Register. If the queue is a master, the waterlevel triggers the data transmission. If a slave,
the waterlevel triggers a flag only and the queue may then be read.
8.2.9 MBIST Control Register
The MBIST is the primary method for memory testing. The MBIST register is one of the few configuration registers with
clear on read on most bits. It is expected that all BIST will be controlled by one location/Port, preventing conflicts that may
develop from interacting ports, making the clear on read a valid operational mode.
Name: CONFIG_REG_MBIST Address: 0x180C8
Bit
Field Name
Type
Reset
Value
Comment
0
MBIST_START
RW
1b0
1
MBIST_EN
RW
1b0
2
I2C_MEM_EN
RW
1b0
7:3
-
0
15:8 MBIST_MEM_ERR RT
8h0
20:16 -
0
21
MB_P1_SR_ME
RT
1b0
Memory BIST Start:
This bit self clears after MBIST is complete
Memory BIST Enable:
This bit is read/write, must stay high during MBIST
I²C Memory Access Enable:
Bits 1 and 2 are XOR
Reserved
Memory BIST Main Memory Block Error:
Block 7 - 0
Reserved
Memory BIST Port 1 / sRIO Memory Error
22
MB_P2_PP_ME
RT
1b0
Memory BIST Port 2 / Parallel Port Memory Error
23
-
0
Reserved
24
MB_DONE
RT
1b0
Memory BIST Done:
If this bit is not “1”, the flags from 8 -25 will not clear on read
25
MB_PASS
RT
1b1
Memory BIST Pass
This bit is meaningful only when bit 24 = 1
31:26 -
0
Reserved
Note:
1.
Table 61 MBIST Control Register
MBIST will start when bit 1 is 1, and bit 0 changes from 0 to 1. Bit 1 will stay at "1" till MBIST is done (bit 24
becomes 1), after that, bit 1 will be self cleared to 0.
8.2.10 QBIST Control Register
The QBIST accompanies the MBIST register. Most bits are clear on read.
93 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.