80KSBR200 Datasheet, PDF (35/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
6.0 Device Programming
The operational setup of the SerB is accomplished through the programming of the configuration registers. During
power up or master reset, the configuration registers default to a known state based upon the configuration established on
the hard-wired pins. After power up, the configuration registers may be further altered through programming. It shall be
possible to hard-wire the SerB to have full port functionality and be fully programmable through any of the designated
programming methods without relying upon a second programming method.
In the priority scheme of configuration, the hard-wired default pin configuration is the dominant configuration during
power up or hard reset. The hard-wired inputs will be read on power up or reset, and shall not alter the state of the SerB
after completion of power up or reset. The hard-wired configuration may be overwritten through any of the programming
schemes, except in a few selected cases (such as designated protocol) where there is no additional programmability.
Once fully powered and hard reset is no longer active, the configuration registers may be reprogrammed or altered by
several schemes. The configuration register will retain the last programmed configuration regardless of programming
method. One programming method is not dominant over the others, except on Master Reset.
The methods of device programming are as follows:
◆ _{Hard wired configuration}
◆ _I2_C
◆ _JTAG
◆ _{sRIO maintenance packets}
The hard-wired configuration will be the initial default setting for the SerB and forced setting after hard reset. The
default configurations are shown in the Configuration Register section.
The configuration registers for the SerB are shown in section 8.2 of this datasheet. All configuration registers may be
read through I²C, JTAG, and sRIO protocol priority packets. In addition to the listed configuration registers, there are many
registers associated with programming sRIO per the sRIO specification. All bits in the configuration registers are readable
by any available method. Bits that have restricted write access may still be read by any method.
6.1 Vendor IDs
For sRIO there are three fixed Device IDs. These are available only when sRIO is active and maybe openly accessed
by any of the register reading mechanisms. If sRIO is not active, this section of the die is not powered, and the IDs are not
available. The sRIO IDs are as follows:
◆ _{The Vendor ID, indicating IDT (assigned by the RapidIO Trade Association)}
◆ _{The Device ID, indicating the part type}
◆ _{The die signature, indicating date code, revision or other assembly specific information}
JTAG also has a JTAG vendor ID. All JTAG IDs are accessible only through JTAG.
6.2 Memory Map
Base Address
sRIO Configuration Registers
0x000000 - 0x0000FC
0x000100 - 0x00053C
0x000600 - 0x000E3C
SerB Configuration Registers
0x018004
0x018008
0x01800C
0x018010
0x018014
Description
RIO Base Feature Space Registers
RIO Extended Feature Space Registers
RIO Error Management Space Registers
Reset & Command Register
Serial Port Configuration Register
reserved for future use
Parallel Port Configuration Register
Memory Allocation Register
Table 1 SerB Memory Map
35 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.