80KSBR200 Datasheet, PDF (158/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Y1
IRQ1
A11
MBDONE
B11
MBPASS
B3
MRST_N
Interrupt 1
(VDD3, GND) / CMOS Output
Memory BIST (VDD, GND) / CMOS Output
Memory BIST (VDD, GND) / CMOS Output
Master Reset (VDD, GND) / CMOS Input
Y17
PLL_OFF
PLL Off
(VDD, GND) / CMOS Input
B10
PPE_N
Parallel Port
(VDD, GND) / CMOS Input
Enable
P18
Q0
QDR SRAM
Data Out 0
(VDDQ, GND) / CMOS Output
R18
Q1
QDR SRAM
Data Out 1
(VDDQ, GND) / CMOS Output
P19
Q2
QDR SRAM
Data Out 2
(VDDQ, GND) / CMOS Output
R19
Q3
QDR SRAM
Data Out 3
(VDDQ, GND) / CMOS Output
T21
Q4
QDR SRAM
Data Out 4
(VDDQ, GND) / CMOS Output
U21
Q5
QDR SRAM
Data Out 5
(VDDQ, GND) / CMOS Output
T22
Q6
QDR SRAM
Data Out 6
(VDDQ, GND) / CMOS Output
U22
Q7
QDR SRAM
Data Out 7
(VDDQ, GND) / CMOS Output
N19
Q8
QDR SRAM
Data Out 8
(VDDQ, GND) / CMOS Output
N18
Q9
QDR SRAM
Data Out 9
(VDDQ, GND) / CMOS Output
R22
Q10
QDR SRAM
Data Out 10
(VDDQ, GND) / CMOS Output
R21
Q11
QDR SRAM
Data Out 11
(VDDQ, GND) / CMOS Output
P22
Q12
QDR SRAM
Data Out 12
(VDDQ, GND) / CMOS Output
P21
Q13
QDR SRAM
Data Out 13
(VDDQ, GND) / CMOS Output
N22
Q14
QDR SRAM
Data Out 14
(VDDQ, GND) / CMOS Output
N21
Q15
QDR SRAM
Data Out 15
(VDDQ, GND) / CMOS Output
Advanced Datasheet*
This is an interrupt output pin whose value is given by the Error
Management Block.
MBIST Done. Set (MBDONE = 1) when MBIST patterns are com-
pleted
MBIST Pass. Set (MBPASS = 1) when MBIST patterns pass.
Cleared (MBPASS = 0) and is sticky when MBIST fails.
SerB Global Reset. Sets all internal registers to default values.
Resets all PLLs. Resets all port configurations. This is a HARD
Reset.
Used for device testing with PLL bypass.
PPE = 0, P-Port is active
PPE = 1, P-Port is powered down and not used (low power).
The QDR Output Data Bus 0
The QDR Output Data Bus 1
The QDR Output Data Bus 2
The QDR Output Data Bus 3
The QDR Output Data Bus 4
The QDR Output Data Bus 5
The QDR Output Data Bus 6
The QDR Output Data Bus 7
The QDR Output Data Bus 8
The QDR Output Data Bus 9
The QDR Output Data Bus 10
The QDR Output Data Bus 11
The QDR Output Data Bus 12
The QDR Output Data Bus 13
The QDR Output Data Bus 14
The QDR Output Data Bus 15
158 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.