80KSBR200 Datasheet, PDF (9/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
1.0 Functional Description
The IDT80KSBR200 is a Serial RapidIO^TM sequential buffer (SerB) flow-control device consisting of up to 18Mbits of
on-chip memory with expansion of one QDR SRAM externally bringing the total buffering capacity to 90Mbits of storage.
This device is built to work with any sRIO device and especially with the IDT Pre-Processing Switch (PPS) number
IDT70K200.
In this configuration, the main application is working in conjunction with the PPS. In applications were multiple DPSs
are used with the PPS, the SerB can function as an over-flow port to handle traffic that is block on any given port or, as a
delay buffer to store data and present it at a later time. This is important in DPS applications were time samples are
compared with the previous sample such as Cellular Base Stations. Please refer to the application note “Serial Buffer and
Pre-Processing Switch”.
The SerB fully complies to the sRIO specification version 1.3 and is implemented to a class 1+ end-point device.
This device operates as a master. In the sRIO environment, a master is defined as a device that originates data trans-
fers, either to or from that device. A slave is one that responds to commands from other devices to move data. As a
master, the SerB can receive data and at a pre-programmed water level (number of packets), the device will form and
transmit either packets or status (e.g., doorbells) to a programmed location.
The SerB performs buffering and off-loading of data as well as buffer-delay of data samples in various environments.
This device can act as a master in which the SerB writes data to a programmed location once the criteria have been meet.
This combination of storage and flexibility make it the perfect buffering solution for sRIO systems.
For applications requiring larger buffers, an additional 72Mbits of QDR SRAM can be attached via the Parallel Port. The
two memories are seamlessly connected by the Serial Buffer to form a large, 90 Mbit buffer memory. The QDR SRAM
interface runs at speeds of only 156.25MHz allowing lower cost memories to be used as well as easier board layout. Data
rates still support up to 10Gbits/s (OC-192) thoughput in the device to maintain full sRIO four-lane compliance.
The device provides Full flag and Empty flag status for the queue for write and read operations respectively. Also a
Programmable Almost Full and Almost Empty flag for the queue is provided.
A JTAG test port is provided running at 3.3V, device has a fully functional Boundary Scan feature, compliant with IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture. The SerB can also be programmed via the JTAG port.
There is also an I²C processor port for programming and retrieving information from the configuration registers.
The device is configured into a single queue comprising the full internal memory and potentially the external memory if
attached. The device treats the full amount of memory, wether internal or a combination of internal and external, as a
single memory block. Status flags from that queue, either referring to the writes (full flags) or the reads (empty flags) to or
from that queue represent the total amount of memory. Flags can be read from the serial port or from the I²C or JTAG port.
Proactive flags can be configured to send a doorbell and/or change the interrupt pin once a flag is set. Partial full and
empty flags can be programmed to provide reaction time for writes and reads respectively. Flags associated with reaching
water marks are available in addition to the full and empty flags.
Further information regarding this device and follow-on devices with added functionality are available from IDT.
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.