80KSBR200 Datasheet, PDF (118/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
12.2.1 Interfacing to Standard-, Fast-, and Hs-mode devices
The SerB supports Fast / Standard (F/S) modes of operation. Per I²C specification, in mixed speed communication the
SerB supports Hs- and Fast-mode devices at 400 kbit/s, and Standard-mode devices at 100 kbit/s. Please refer to the I²C
specification for detail on speed negotiation on a mixed speed bus.
12.2.2 SerB Specific Memory Access
There is a SerB-specific I²C memory access implementation. This implementation is fully I²C compliant. It requires the
memory address to be explicitly specified during writes. This provides directed memory accesses through the I²C bus.
Subsequent reads always begin at the address specified during the last write.
The write procedure requires the 3-Bytes (22-bits) of memory address to be provided following the device address.
Thus, the following are required: device address – one or two bytes depending on 10-bit/7-bit addressing, memory address
– 3 bytes yielding 22-bits of memory address, and a 32-bit data payload – 4 byte words.
The read procedure has the memory address section of the transfer removed. Thus, to perform a read, the proper
access would be to perform a write operation and issue a repeated start after the acknowledge bit following the third byte
of memory address. Then, the master would issue a read command selecting the SerB through the standard device
address procedure with the R/W bit high. Note that in 10-bit device address mode (ADS=1), only the two MSBs need be
provided during this read. Data from the previously loaded address would immediately follow the device address protocol.
It is possible to issue a stop or repeated start anytime during the write data payload procedure, but must be before the final
acknowledge (i.e. canceling the write before the actual write operation is completed and performed). Also, the master
would be allowed to access other devices attached to the I²C bus before returning to select the SerB for the subsequent
read operation from the loaded address.
12.3 Figures
R/W Bit (R=1, W=0)
Data output is from base mem_addr[21:0]
8
1110
1A
17
26
35
44
A
A
A
A
Device
Address
[9:8]
Data
Word #1
MSB Byte
Data
Word #1
Byte #2
Data
Word #1
Byte #3
Data
Word #1
LSB Byte
5686 drw05
Note:
1.
Figure 16 Write protocol with 10-bit Slave Address (ADS =1)
I²C writes to memory align on 32-bit word boundaries, thus the 22 address MSBs must be provided while the
2 LSBs associated with word and byte pointers are DON’T CARE and are therefore not transmitted.
R/W Bit (R=1, W=0)
8
11 10
1A
Device
Address
[9:8]
Data
Word #1
MSB Byte
Data output is from base mem_addr[21:0]
17
26
35
A
A
A
Data
Word #1
Byte #2
Data
Word #1
Byte #3
44
A
Data
Word #1
LSB Byte
Figure 17 Read Protocol with 10-bit Slave Address (ADS=1)
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.