80KSBR200 Datasheet, PDF (117/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
12.0 I²C-Bus
The SerB is compliant with the I²C specification [1]. This specification provides all functional detail and electrical speci-
fications associated with the I²C bus. This includes signaling, addressing, arbitration, AC timing, DC specifications, and
other details.
The I²C bus is comprised of Serial Data (SDA) and Serial Clock (SCL) pins and can be used to attach a CPU for initial-
ization and management purposes. A CPU can then access registers and program the device, but it cannot access other
devices attached to the sRIO interfaces through the I²C bus. The I²C interface supports Fast/Standard (F/S) mode (400/
100 kHz). The SerB does NOT support CBUS or General Address calls.
12.1 I²C Device Address
Relative to I²C, the SerB is a slave-only receiver and transmitter. The device address for the SerB is fully pin-defined by
10 external pins. This provides full flexibility in defining the slave address to avoid conflicting with other I²C devices on a
given bus. The SerB may be operated as either a 10-bit addressable device or a 7-bit addressable device based on
another external pin Address Select (ADS). If the ADS pin is tied to Vdd, then the SerB operates as a 10-bit addressable
device and the device address will be defined as ID[9:0]. If the ADS pin is tied to GND, then the SerB operates as a 7-bit
addressable device with the device address defined by ID[6:0]. The addressing mode must be established at power-up
and remain static throughout operation. Dynamic changes will result in undetermined behavior.
Pin
I²C Address Bit (pin_addr)
ID0
0
ID1
1
ID2
2
ID3
3
ID4
4
ID5
5
ID6
6
ID7
7 (don’t care in 7-bit mode)
ID8
8 (don’t care in 7-bit mode)
ID9
9 (don’t care in 7-bit mode)
Table 101 I²C static address selection pin configuration
All of the SerB’s registers are addressable through I²C. These registers are accessed via 22-bit addresses and 32-bit
word boundaries though standard reads and writes. These registers may also be accessed through the sRIO and JTAG
interfaces.
12.2 Signaling
The SerB is a slave-only receive and transmit device. Thus, communication with the SerB on the I²C bus follows these
two cases:
1. Suppose a master device wants to send information to the SerB:
– Master device addresses SerB (slave)
– Master device (master-transmitter), sends data to SerB (slave- receiver)
– Master device terminates the transfer
2. If a master device wants to receive information from the SerB:
– Master device addresses SerB (slave)
– Master device (master-receiver) receives data from SerB (slave- transmitter)
– Master device terminates the transfer.
All signaling is fully compliant with I²C. Full detail of signaling can be found in the I²C specification [1].
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.