80KSBR200 Datasheet, PDF (120/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
At recommended operating conditions with VDD3 = 2.5V ± 100mV
Advanced Datasheet*
Figure 21 I²C SDA & SCL DC Electrical Specifications
12.5 I²C AC Electrical Specifications
Note:
1.
2.
3.
4.
Figure 22 Specifications of the SDA and SCL bus lines for F/S-mode I²C -bus devices
For more information, see the I2C-Bus specification by Philips Semiconductor [1].
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the
SCL signal) to bridge the undefined region of the falling edge of SCL.
The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL
signal.
A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement tSU;DAT >
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of
the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line tRMAX + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I²C-bus specifi-
cation) before the SCL line is released.
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
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