80KSBR200 Datasheet, PDF (73/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Note:
1. The above register is described in the RIO Specification Part 6, sec. 6.6.2.3
Advanced Datasheet*
Port General Control CSR
The port general control register contains control register bits applicable to all ports on a processing element.
Name: PORT_GEN_CTRL_CSR Address: 0x00013C
Bit
Field Name
Reset
Value
Comment
28:0
-
0
Reserved.
29
DISCOVER
30
MSTR_EN
31
HOST
1b0
Discovered:
This device has been located by the processing element responsible
for system configuration.
0b0 - The device has not been previously discovered.
0b1 - The device has been discovered by another processing ele-
ment.
1b0
Master Enable:
The master enable bit controls whether or not a device is allowed to
issue requests into the system. If the Master Enable is not set, the
device may only respond to requests.
0b0 - processing element cannot issue requests.
0b1 - processing element can issue requests.
1b0
Host:
A host device is a device that is responsible for system exploration,
initialization, and maintenance. Agent or slave devices are typically
initialized by Host devices.
0b0 - agent or slave device.
0b1 - host device.
Note:
1.
Table 29 Port General Control CSR
The above register is described in the RIO Specification Part 6, sec. 6.6.2.4
Port 0 Link Maintenance Request CSR
The port 0 link maintenance request register is accessible both by a local processor and an external device. A write to
this register generates a link-request control symbol on the corresponding RIO port interface. Care should be taken when
writing this register that it is only used for hot swap and not for software assisted error recovery (which is not supported).
Name: P0_LNK_MAINT_REQ_CSRAddress: 0x000140
Bit
Field Name
Reset
Value
Comment
2:0
CMD
3b000
Command:
LINK_REQUEST command to send. If read, this field returns the last
written value. If written with a value other than 3b011 (reset-device)
or 3b100 (input-status), resulting operation will be undefined, as all
other values are reserved in the RIO spec.
31:3
-
0
Reserved.
Note:
1.
Table 30 Port 0 Link Maintenance Request CSR
The above register is described in the RIO Specification Part 6, sec. 6.6.2.5
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
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