80KSBR200 Datasheet, PDF (119/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
R/W Bit (R=1, W=0)
8
1A
Device
Address
[6:0]
Data
Word #1
MSB Byte
Data output is from base mem_addr[21:0]
17
26
35
A
A
A
Data
Word #1
Byte #2
Data
Word #1
Byte #3
Data
Word #1
LSB Byte
5686 drw06
Note:
1.
Figure 18 Write protocol with 7-bit Slave Address (ADS=0)
I²C writes to memory align on 32-bit word boundaries, thus the 22 address MSBs must be provided while the
2 LSBs associated with word and byte pointers are DON’T CARE and are therefore not transmitted.
R/W Bit (R=1, W=0)
8
1A
Device
Address
[6:0]
Data
Word #1
MSB Byte
Data output is from base mem_addr[21:0]
17
26
35
A
A
A
Data
Word #1
Byte #2
Data
Word #1
Byte #3
Data
Word #1
LSB Byte
Figure 19 Read protocol with 7-bit Slave Address (ADS=0)
12.4 I²C DC Electrical Specifications
Note that the ADS and ID pins will all run off the core (1.2V) power supply, and these pins are required to be fixed
during operation. Thus, these pins must be statically tied to the 1.2V supply or GND.
Tables 19 and 20 below lists the SDA and SCL electrical specifications for F/S-mode I²C devices:
At recommended operating conditions with VDD3 = 3.3V ± 5%
Figure 20 I²C SDA & SCL DC Electrical Specifications
119 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.