80KSBR200 Datasheet, PDF (146/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
16.2 Pin Listing
Table 108 Pin Listing (Alphabetical)
Advanced Datasheet*
Pin
Number
Pin Name
Function
V17
A0
QDR ADDR 0
Supply / Interface
(VDDQ, GND) / CMOS Output
AB19
A1
QDR ADDR 1 (VDDQ, GND) / CMOS Output
W17
A2
QDR ADDR 2 (VDDQ, GND) / CMOS Output
AB20
A3
QDR ADDR 3 (VDDQ, GND) / CMOS Output
AA18
A4
QDR ADDR 4 (VDDQ, GND) / CMOS Output
AA20
A5
QDR ADDR 5 (VDDQ, GND) / CMOS Output
Y18
A6
QDR ADDR 6 (VDDQ, GND) / CMOS Output
AA21
A7
QDR ADDR 7 (VDDQ, GND) / CMOS Output
W18
A8
QDR ADDR 8 (VDDQ, GND) / CMOS Output
Y20
A9
QDR ADDR 9 (VDDQ, GND) / CMOS Output
W19
A10
QDR ADDR 10 (VDDQ, GND) / CMOS Output
Y21
A11
QDR ADDR 11 (VDDQ, GND) / CMOS Output
V19
A12
QDR ADDR 12 (VDDQ, GND) / CMOS Output
AA22
A13
QDR ADDR 13 (VDDQ, GND) / CMOS Output
Pin Function Description
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
146 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.