80KSBR200 Datasheet, PDF (147/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
AA19
A14
QDR ADDR 14 (VDDQ, GND) / CMOS Output
Y22
A15
QDR ADDR 15 (VDDQ, GND) / CMOS Output
V21
A16
QDR ADDR 16 (VDDQ, GND) / CMOS Output
W22
A17
QDR ADDR 17 (VDDQ, GND) / CMOS Output
V18
A18
QDR ADDR 18 (VDDQ, GND) / CMOS Output
V22
A19
QDR ADDR 19 (VDDQ, GND) / CMOS Output
U18
A20
C6
ADS
QDR ADDR 20 (VDDQ, GND) / CMOS Output
I²C
(VDD, GND) / CMOS Input
U3
AUXCKI
AUX ClockI
V3
AUXCKQ
AUX ClockQ
E21
CKI
P-Port Clock (VDD, GND) / CMOS Input
E22
CKI_N
P-Port Clock (VDD, GND) / CMOS Input
H18
CKO
Echo Clock
(VDD, GND) / CMOS Output
G18
CKO_N
Echo Clock
(VDD, GND) / CMOS Output
Advanced Datasheet*
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
I²C address width select. Set ADS = GND for 7-bit SerB slave
address. ADS = Vdd for 10-bit. NOTE: SUPPLY / LEVELS
REQUIREMENTS ARE UNQUE FROM THE OTHER I²C PINS.
Auxiliary clocks provided to bypass CDR block for DC-type test-
ing of SERDES RX inputs.
Auxiliary clocks provided to bypass CDR block for DC-type test-
ing of SERDES RX inputs.
Clock input for the P-Port. These inputs should be connected to
the CQ/nCQ outputs of the QDR SRAM when operating as a
FIFO controller.
Clock input for the P-Port. These inputs should be connected to
the CQ/nCQ outputs of the QDR SRAM when operating as a
FIFO controller.
Clock output that is closely aligned with parallel port data output
(Q), address (A), Queue Empty (E), and Queue Full (F). When
operating as a FIFO controller, outputs read (nRd), and write
(nWr) are also aligned. The alignment is selectable as either cen-
ter aligned or edge aligned in the configuration register. When
PPM is LOW, this output should be connected to the K and nK
inputs of the QDR SRAM.
Clock output that is closely aligned with parallel port data output
(Q), address (A), Queue Empty (E), and Queue Full (F). When
operating as a FIFO controller, outputs read (nRd), and write
(nWr) are also aligned. The alignment is selectable as either cen-
ter aligned or edge aligned in the configuration register. When
PPM is LOW, this output should be connected to the K and nK
inputs of the QDR SRAM.
147 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.