80KSBR200 Datasheet, PDF (139/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
15.5 Instruction Register (IR)
The Instruction register allows an instruction to be shifted serially into the SerB at the rising edge of TCK. The instruc-
tion is then used to select the test to be performed or the test register to be accessed, or both. The instruction shifted into
the register is latched at the completion of the shifting process, when the TAP controller is at the Update-IR state.
The Instruction Register contains four shift-register-based cells that can hold instruction data. This register is decoded
to perform the following functions:
◆ _{To select test data registers that may operate while the instruction is current. The other test data registers}
should not interfere with chip operation and selected data registers.
◆ _{To define the serial test data register path used to shift data between TDI and TDO during data register}
scanning.
The Instruction Register is comprised of 4 bits to decode instructions, as shown in the table below.
Instruction
Definition
OPcode
[3:0]
EXTEST
Mandatory instruction allowing the testing of board level interconnections. Data is typi- 0000
cally loaded onto the latched parallel outputs of the boundary scan shift register using
the SAMPLE/PRELOAD instruction prior to use of the EXTEST instruction. EXTEST
will then hold these values on the outputs while being executed. Also see the CLAMP
instruction for similar capability.
SAMPLE/
PRELOAD
IDCODE
Mandatory instruction that allows data values to be loaded onto the latched parallel out- 0001
put of the boundary-scan shift register prior to selection of the other boundary-scan test
instruction. The Sample instruction allows a snapshot of data flowing from the system
pins to the on-chip logic or vice versa.
Provided to select Device Identification to read out manufacturer’s identity, part, and 0010
version number.
HIGHZ
CLAMP
Tri-states all output and bidirectional boundary scan cells.
0011
Provides JTAG user the option to bypass the part’s JTAG controller while keeping the 0100
part outputs controlled similar to EXTEST.
EXTEST_PULSE
EXTEST_TRAIN
RESERVED
AC Extest instruction implemented in accordance with the requirements of the IEEE 0101
std. 1149.6 specification.
AC Extest instruction implemented in accordance with the requirements of the IEEE 0110
std. 1149.6 specification.
Behaviorally equivalent to the BYPASS instruction as per the IEEE std. 1149.1 specifi- 0111 — 1001
cation. However, the user is advised to use the explicit BYPASS instruction.
CONFIGURA-
TION REGISTER
ACCESS (CRA)
SerB-specific opcode to allow reading and writing of the configuration registers. Reads 1010
and writes must be 32-bits. See further detail below.
PRIVATE
SHIFT FUSE
STATUS
For internal use only. Do not use.
To shift the internal fuse status out to TDO pin.
1011 — 1100
1101
PRIVATE
BYPASS
For internal use only. Do not use.
1110
The BYPASS instruction is used to truncate the boundary scan register as a single bit in 1111
length.
Table 104 Instructions Supported By 80KSBR200’s JTAG Boundary Scan
15.5.1 EXTEST
The external test (EXTEST) instruction is used to control the boundary scan register, once it has been initialized using
the SAMPLE/PRELOAD instruction. Using EXTEST, the user can then sample inputs from or load values onto the external
pins of the 80KSBR200. Once this instruction is selected, the user then uses the SHIFT-DR TAP controller state to shift
values into the boundary scan chain. When the TAP controller passes through the UPDATE-DR state, these values will be
latched onto the output pins or into the output enables.
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.