80KSBR200 Datasheet, PDF(106/172 Page) Integrated Device Technology

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80KSBR200 Datasheet, PDF (106/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

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IDT 80KSBR200

Notes

Note:

Advanced Datasheet*

Memory Stop - The sRIO memory address has incremented to or beyond the stop address. This flag may

be used to send a doorbell if the address reaches the stop address (triggering the flag condition), the flag

will remain active until software writes a â1â to clear the flag.

Tally1 - The packet tally counter will wrap. If the user whishes to know it wrapped, the flag may be used.

8.5.6 Missing 2 Packet Flag Register

If missing 2 packet is turned on and two or more packets are missing, the flags of this register will be used. Note that If

this register is read and cleared, the âMissing Packet Address Logging Register 1â will also be cleared.

Name: MISS2_PKT_FLAG

MISS2_PKT_MASK

Address: 0x19C50

0x19D10

If this register generates an sRIO packet, the packet will be a doorbell.

7-1

11-10

15-12

23-16

31-24

39-32

47-40

55-48

63-56

Note:

Signal

MISSIN2

WR32

PRIO

DESTID

MASK

Stat Description

CL Two or more sRIO packets were detected as missing

Reserved

RW Defines whether the sRIO doorbell is an 8 or 16 bit destination ID

RW 0 = Write 8 bits (clear flags only), 1 = Write 32 bits (write new dest IDs)

RW Priority for Doorbell packet

Unused bits

RW Destination ID for sRIO Doorbell

RW Destination ID for sRIO Doorbell, for 16 bit extension

RW S-Port Doorbell Mask

Unused bits

RW Interrupt 0 Mask

RW Interrupt 1 Mask

Table 89 Missing Packet Flag Register

Missing 2 - If two or more packets are missing, they cannot be replaced. This flag indicates that a

catastrophic error has occurred in the PPS application.

8.5.7 FIFO Empty Flag Register

If this register generates an sRIO packet, the packet will be a doorbell.

Name: FIFO_EMPTY_FLAG

FIFO_EMPTY_MASK

Address: 0x19C60

0x19D20

Signal

Stat Description

RT Queue 0, Empty Flag

PAE

RT Queue 0, Programmable Almost Empty

RT Queue 0, Packet Ready

RT Queue 0, Waterlevel Exceeds Packet Count

7-4

Reserved

Table 90 FIFO Queue Empty Flag Register

106 of 172

March 19, 2007

â2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a

Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.

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