80KSBR200 Datasheet, PDF (84/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
Bit
Field Name
Reset
Value
Comment
1
UNS_ACK_SYM_E 1b0
N
2
DELIN_ERR_EN 1b0
3
-
0
Unsolicited Acknowledge Control Symbol Enable:
Enable error rate counting of unsolicited acknowledge control sym-
bol errors.
Delineation Error Enable:
Enable error rate counting of delineation errors.
Reserved.
4
PROTO_ERR_EN 1b0
5
NOUT_ACKID_EN 1b0
16:6
-
0
17
RCV_PKT_EXC_E 1b0
N
18
RCV_BAD_CRC_E 1b0
N
19
RCV_PKT_ACK_E 1b0
N
20
RCV_PKT_SYM_E 1b0
N
Protocol Error Enable:
Enable error rate counting of protocol errors.
Non-outstanding ackID Enable:
Enable error rate counting of link-response received with an ackID
that is not outstanding.
Reserved.
Received Packet Exceeds 276 Bytes:
Enable error rate counting of packet which exceeds the maximum
allowed size.
Received Packet with bad CRC Enable:
Enable error rate counting of packet with a bad CRC value.
Received Packet with Unexpected ackID Enable:
Enable error rate counting of packet with unexpected ackID value
(out-of-sequence ackID).
Received Packet-not-accepted Control Symbol Enable:
Enable error rate counting of received packet-not-accepted control
symbols.
21
RCV_ACK_SYM_E 1b0
N
22
RCV_CC_SYM_EN 1b0
31:23 -
0
Received Acknowledge Control Symbol with Unexpected ackID
Enable:
Enable error rate counting of an acknowledge control symbol with an
unexpected ackID.
Received Corrupt Control Symbol Enable:
Enable error rate counting of a corrupt control symbol.
Reserved.
Note:
1.
Table 43 Port 0 Error Rate Enable CSR
The above register is described in the RIO Specification Part 8, sec. 2.3.2.11
Port 0 Attribute Capture CSR
The error capture attribute register indicates the type of information contained in the port n error capture registers. In
the case of multiple detected errors during the same clock cycle one of the errors must be reflected in the Error type field.
The error that is reflected is implementation dependent. Undefined results will occur if this register is written while actual
physical layer errors are being detected by the port. Also, there could be latency between asserting an interrupt from
Output-Degraded Encountered or Output-Failed Encountered to loading this register, such that the interrupt is asserted a
few cycles before the error is captured into this register.
84 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.