80KSBR200 Datasheet, PDF (86/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
Port 0 Packet Capture 1 CSR
Error capture register 1 contains bytes 4 through 7 of the packet header. Undefined results will occur if this register is
written while actual physical layer errors are being detected by the port. Also, there could be latency between asserting an
interrupt from Output-Degraded Encountered or Output-Failed Encountered to loading this register, such that the interrupt
is asserted a few cycles before the error is captured into this register.
Name: P0_PKT_CAP_1_CSR Address: 0x000650
Bit
Field Name
Reset
Value
Comment
31:0
CAPT_1
All 0s
Capture 1: Control character and control symbol or Bytes 4 to 7 of
Packet Header.
Note:
1.
Table 46 Port 0 Packet/Control Symbol Capture 1 CSR
The above register is described in the RIO Specification Part 8, sec. 2.3.2.14
Port 0 Packet Capture 2 CSR
Error capture register 2 contains bytes 8 through 11 of the packet header. Undefined results will occur if this register is
written while actual physical layer errors are being detected by the port. Also, there could be latency between asserting an
interrupt from Output-Degraded Encountered or Output-Failed Encountered to loading this register, such that the interrupt
is asserted a few cycles before the error is captured into this register
Name: P0_PKT_CAP_2_CSR Address: 0x000654
Bit
Field Name
Reset
Value
Comment
31:0
CAPT_2
All 0s
Capture 2: Control character and control symbol or Bytes 8 to 11 of
Packet Header.
Note:
1.
Table 47 Port 0 Packet/Control Symbol Capture 2 CSR
The above register is described in the RIO Specification Part 8, sec. 2.3.2.15
Port 0 Packet Capture 3 CSR
Error capture register 3 contains bytes 12 through 15 of the packet header. Undefined results will occur if this register is
written while actual physical layer errors are being detected by the port. Also, there could be latency between asserting an
interrupt from Output- Degraded Encountered or Output-Failed Encountered to loading this register, such that the interrupt
is asserted a few cycles before the error is captured into this register.
Name: P0_PKT_CAP_3_CSR Address: 0x000658
Bit
Field Name
Reset
Value
Comment
31:0
CAPT_3
All 0s
Capture 3: Control character and control symbol or Bytes 12 to 15 of
Packet Header.
Note:
1.
Table 48 Port 0 Packet/Control Symbol Capture 3 CSR
The above register is described in the RIO Specification Part 8, sec. 2.3.2.16
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March 19, 2007
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