80KSBR200 Datasheet, PDF (160/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
V21
RDO_N
Read Strobe (VDD, GND) / CMOS Output
AB3
REFCLKN
SERDES Clock (VDD, GND) / Differential Input
AA3
REFCLKP
SERDES Clock (VDD, GND) / Differential Input
V1
REXTN
Rext
U1
REXTP
Rext
L1
S1_RXN0
Port 1 Receive (VDDS, GNDS) /
S-Port 1 Differential Input
M1
S1_RXP0
Port 1 Receive (VDDS, GNDS) /
S-Port 1 Differential Input
L4
S1_RXN1
Port 1 Receive (VDDS, GNDS) /
S-Port 1 Differential Input
L3
S1_RXP1
Port 1 Receive (VDDS, GNDS) /
S-Port 1 Differential Input
J1
S1_RXN2
Port 1 Receive (VDDS, GNDS) /
S-Port 1 Differential Input
H1
S1_RXP2
Port 1 Receive (VDDS, GNDS) /
S-Port 1 Differential Input
J4
S1_RXN3
Port 1 Receive (VDDS, GNDS) /
S-Port 1 Differential Input
J3
S1_RXP3
Port 1 Receive (VDDS, GNDS) /
S-Port 1 Differential Input
P1
S1_TXN0
Port1 Transmit (VDDS, GNDS) /
S-Port 1 Differential Output
P2
S1_TXP0
Port1 Transmit (VDDS, GNDS) /
S-Port 1 Differential Output
P4
S1_TXN1
Port1 Transmit (VDDS, GNDS) /
S-Port 1 Differential Output
N4
S1_TXP1
Port1 Transmit (VDDS, GNDS) /
S-Port 1 Differential Output
F1
S1_TXN2
Port1 Transmit (VDDS, GNDS) /
S-Port 1 Differential Output
F2
S1_TXP2
Port1 Transmit (VDDS, GNDS) /
S-Port 1 Differential Output
F4
S1_TXN3
Port1 Transmit (VDDS, GNDS) /
S-Port 1 Differential Output
G4
S1_TXP3
Port1 Transmit (VDDS, GNDS) /
RIO Differential Output
Advanced Datasheet*
When QDR type SRAM attached, this output should be con-
nected to the /Rd input on the QDR SRAM(s). The FIFO control-
ler will use this pin to control the read function on the SRAM.
Negative side of differential input clock. This clock is used as the
156MHz reference for standard SERDES operation.
Positive side of differential input clock. This clock is used as the
156MHz reference for standard SERDES operation.
External bias resistor. This pin must be connected to Rextp with a
12k Ohm resistor. This establishes the drive bias on the SERDES
output. This provides CML driver stability across process and
temperature.
External bias resistor. This pin must be connected to Rextn with a
12k Ohm resistor.
Negative end of differential receiver, S-Port, Lane 0
Positive end of differential receiver, S-Port, Lane 0
Negative end of differential receiver, S-Port, Lane 1
Positive end of differential receiver, S-Port, Lane 1
Negative end of differential receiver, S-Port, Lane 2
Positive end of differential receiver, S-Port, Lane 2
Negative end of differential receiver, S-Port, Lane 3
Positive end of differential receiver, S-Port, Lane 3
Negative end of differential transmitter, S-Port, Lane 0
Positive end of differential transmitter, S-Port, Lane 0
Negative end of differential transmitter, S-Port, Lane 1
Positive end of differential transmitter, S-Port, Lane 1
Negative end of differential transmitter, S-Port, Lane 2
Positive end of differential transmitter, S-Port, Lane 2
Negative end of differential transmitter, S-Port, Lane 3
Positive end of differential transmitter, S-Port, Lane 3
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.