80KSBR200 Datasheet, PDF (135/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
15.0 JTAG Interface
The 80KSBR200 offers full JTAG (Boundary Scan) support for both its slow speed and high speed pins. This allows
“pins-down” testing of newly manufactured printed circuit boards as well as troubleshooting of field returns. The JTAG TAP
interface also offers an alternative method for Configuration Register Access (CRA) (along with the sRIO and I²C ports).
Thus this port may be used for programming the SerB’s many registers.
Boundary scan testing of the AC-coupled IOs is performed in accordance with IEEE 1149.6 (AC Extest).
15.1 IEEE 1149.1 (JTAG) & IEEE 1149.6 (AC Extest) Compliance
All DC pins are in full compliance with IEEE 1149.1 [10]. All AC-coupled pins fully comply with IEEE 1149.6 [11]. All
1149.1 and 1149.6 boundary scan cells are on the same chain. No additional control cells are provided for independent
selection of negative and/or positive terminals of the TX- or RX-pairs.
15.2 System Logic TAP Controller Overview
The system logic utilizes a 16-state, six-bit TAP controller, a four-bit instruction register, and five dedicated pins to
perform a variety of functions. The primary use of the JTAG TAP Controller state machine is to allow the five external JTAG
control pins to control and access the SerB's many external signal pins. The JTAG TAP Controller can also be used for
identifying the device part number. The JTAG logic of the 80KSBR200 is depicted in the figure below.
TDI
TMS
TCK
TRST
Boundary Scan Register
Device ID Register
Bypass Register
Instruction Register Decoder
4-Bit Instruction Register
Tap Controller
m
u
x
m ^TDO
u
x
Figure 41 Diagram of the JTAG Logic
15.3 Signal Definitions
JTAG operations such as Reset, State-transition control and Clock sampling are handled through the signals listed in
the table below. A functional overview of the TAP Controller and Boundary Scan registers is provided in the sections
following the table.
Pin Name Type
Description
TRST
TCK
Input JTAG RESET
Asynchronous reset for JTAG TAP controller (internal pull-up)
Input JTAG Clock
Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output
on the falling edge.
TMS
Input JTAG Mode Select. Requires an external pull-up.
Controls the state transitions for the TAP controller state machine (internal pull-up)
Table 103 JTAG Pin Descriptions (Part 1 of 2)
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.