80KSBR200 Datasheet, PDF (162/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
A14
TM0
B13
TM1
A12
TM2
A3
TMS
A4
TRST
C22
VDD
D2
VDD
D4
VDD
D11
VDD
D13
VDD
E6
VDD
E8
VDD
E10
VDD
E12
VDD
E14
VDD
E20
VDD
F7
VDD
F9
VDD
F11
VDD
F13
VDD
F17
VDD
G6
VDD
G8
VDD
TMODE0
(VDD3, GND) / CMOS Input
TMODE1
TMODE2
JTAG
JTAG
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
(VDD3, GND) / CMOS Input
(VDD3, GND) / CMOS Input
(VDD3, GND) / CMOS Input
(VDD3, GND) / CMOS Input
Advanced Datasheet*
TM[2:0]; MBIST Enable for use in testing on-chip memories.
MBIST is enabled when mben = 1. Internal pull-down ensures
disable if this pin is not driven.
TM[2:0]; MBIST Enable for use in testing on-chip memories.
TM[2:0]; MBIST Enable for use in testing on-chip memories.
JTAG Tap Port Mode Select
JTAG Tap Port Asynchronous Reset
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
162 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.