80KSBR200 Datasheet, PDF (68/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
Bit
Field Name
Reset
Value
Comment
11
DATA_MSG
1b0
12
NWR_W_RESP
1b1
13
STRM_WR
1b1
Data Message:
PE can support a data message operation.
NWRITE_R:
PE support a Nwrite_R operation.
Streaming Write:
PE support an Swrite operation.
14
NWRITE
15
NREAD
31:16 -
1b1
NWRITE:
PE support a Nwrite operation.
1b1
NREAD:
PE support a Nread operation.
0
Reserved.
Note:
1.
Table 19 Destination Operations CAR
The above register is described in the RIO Specification Part 1, sec. 5.4.8, Part 2, sec. 5.4.2, Part 5, sec. 5.4.2,
Part 10, sec. 5.4.2
8.1.5 Command and Status Registers
The SerB contains a set of Command and Status Registers (CSRs) that allows an external processing element to
control and determine the status of its internal hardware. All registers are 32 bits wide and are organized and accessed in
the same way as the CARs.
Refer to Table 5-2 of the RIO Input/Output Logical Specification in Chapter 5 for the required behavior for accesses to
reserved registers and register bits.
Processing Element Logical Layer Control CSR
PELLCCSR controls the extended addressing abilities. SerB will only support 34-bit addressing.
PELLCCSR is a read only register.
Name: PROC_ELMT_CTRL_CSRAddress: 0x00004C
Bit
Field Name
Reset
Value
Comment
2:0
EXT_ADDR_CTRL 3b001
31:3
-
0
Extended Addressing Control (read-only):
Controls the number of address bits generated by the PE as a
source and processed by the PE as the target of an operation.
3b100 - PE supports 66 bit addresses
3b010 - PE supports 50 bit addresses
3b001 - PE supports 34 bit addresses (default)
All other encoding reserved.
Reserved.
Note:
1.
Table 20 Processing Element Logical Layer Control CSR
The above register is described in the RIO Specification Part 1, sec. 5.5.1
Local Configuration Space Base Address 1 CSR
The local configuration space base address 1 command and status register specifies the least significant bits of the
local physical address double-word offset for the processing element’s configuration register space, allowing the configura-
tion register space to be physically mapped in the processing element. This register allows configuration and maintenance
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.