80KSBR200 Datasheet, PDF (128/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
Figure 33 Receiver AC Timing Specifications - 1.25 GBaud
Note:
1.
Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal
jitter. The sinusoidal jitter may have any amplitude and frequency in the un-shaded region of Figure 35. The
sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and
other variable system effects
Note:
1.
Figure 34 Receiver AC Timing Specifications - 2.5 GBaud
Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal
jitter. The sinusoidal jitter may have any amplitude and frequency in the un-shaded region of Figure 35. The
sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and
other variable system effects.
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.