80KSBR200 Datasheet, PDF (24/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
◆ _{srcTID = the Transaction ID for sRIO end to end retransmissions (generated at the interface)}
◆ _{Hop Count = Set to 0xFF to initiate the hop count}
◆ _{Payload = 32 bits of data read from the designated register}
◆ _{CRC = 16 bits of CRC}
3.4.10 Virtual Channel Handler
There is no virtual channel handler in the SerB. Virtual channels do not appear beyond the sRIO interface and have no
affect on SerB operation.
3.5 sRIO Control Symbols
The sRIO control symbols are described in the sRIO Part 6: 1x/4x LP-Serial Physical Layer Specification in Chapter 3.
Of particular note, these symbols are used to acknowledge all sRIO packets. The SerB shall support the following Stype 0
control symbols.
◆ _{Packet Accepted}
◆ _{Packet Retry}
◆ _{Packet Not Accepted}
◆ _Status
◆ _{Link Response}
These control symbols shall be used to acknowledge all incoming sRIO packets and doorbells. Outgoing packets and
doorbells shall expect a response and report errors when they occur.
3.6 Use of CRC and CRC Errors
The SerB shall have the capability of using CRC-16 and is defined in the sRIO "1x/4x LP-Serial Physical Layer Specifi-
cation" in section 2.4.2.
The following rules dictate uses of CRC within the SerB:
◆ _{CRC will be CRC-16 with two bytes in size.}
◆ _{CRC errors shall be counted. The counts shall be stored and readable through the configuration registers.}
◆ _{If retransmission is turned off, a packet with CRC errors shall be dropped. There is no indication a bad packet}
was received. The CRC error will be logged. The user may use higher level detection to retransmit a section of
data.
◆ _{All CRC errors will set the error flag and may cause interrupts or doorbells per the flag configuration.}
◆ _{sRIO contains CRC in all packets. CRC suppression is used with the PPS.}
◆ _{The minimum packet size when retransmit is turned on is 8 bytes payload.}
3.7 Parallel Port Interface
The P-Port is a standard parallel interface that is used to drive QDRII SRAM devices. It has a 36-bit data bus, and other
control signals that may be connected to a standard QDRII memory interface.
The SerB parallel port options:
◆ _{The SerB may act as a FIFO controller, using an external QDRII-B4 x36 memory as extra storage space that}
may be allocated to the internal FIFO queue as desired.
◆ _{P-Port may be disabled, either by a pin, or by programming an internal register.}
The definition of the P-Port interface in this specification is guidance only. The overriding requirement is that the SerB
must connect to a QDRII-B4, x36 device.
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.