80KSBR200 Datasheet, PDF (7/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
List of Figures
Advanced Datasheet*
Figure 1: Diagram of SerB Interfaces
10
Figure 2: PPS Data Storage
13
Figure 3: Generic sRIO Request Packet
18
Figure 4: sRIO Physical Layer Header
19
Figure 5: Transaction Types (8 or 16)
19
Figure 6: Transaction ID Range for sRIO Packet Generating Entities
22
Figure 7: sRIO Maintenance Request Packet (Type 8)
23
Figure 8: sRIO Maintenance Response Packet (Type 8)
23
Figure 9: Typical sRIO Packet showing location of Source and Destination IDs
27
Figure 10: sRIO Doorbell Packet
33
Figure 11: Reset Timeline
111
Figure 12: REF_CLK Representative Circuit
113
Figure 13: AC Output Test Load (JTAG)
115
Figure 14: AC Output Test Load (I2C)
116
Figure 15: sRIO Lanes Test Load
116
Figure 16: Write Protocol with 10-bit Slave Address (ADS = 1)
118
Figure 17: Read Protocol with 10-bit Slave Address (ADS = 1)
118
Figure 18: Write Protocol with 7-bit Slave Address (ADS = 0)
119
Figure 19: Read Protocol with 7-bit Slave Address (ADS = 0)
119
Figure 20: I2C SDA & SCL DC Electrical Specifications (VDD3 = 3.3V)
119
Figure 21: I2C SDA & SCL DC Electrical Specifications (VDD3 = 2.5V)
120
Figure 22: Specification of the SDA & SCL bus lines for F/S-mode I2C-bus Device
120
Figure 23: I2C Timing Waveform
121
Figure 24: Differential Peak-Peak Voltage of Transmitter or Receiver
123
Figure 25: Short Run Transmitter AC Timing Specifications - 1.25 GBaud
124
Figure 26: Short Run Transmitter AC Timing Specifications - 2.5 GBaud
125
Figure 27: Short Run Transmitter AC Timing Specifications - 3.125 GBaud
125
Figure 28: Long Run Transmitter AC Timing Specifications - 1.25 GBaud
125
Figure 29: Long Run Transmitter AC Timing Specifications - 2.5 GBaud
126
Figure 30: Long Run Transmitter AC Timing Specifications - 3.125 GBaud
126
Figure 31: Transmitter Output Compliance Mask
127
Figure 32: Transmitter Differential Output Eye Diagram Parameters
127
Figure 33: Receiver AC Timing Specifications - 1.25 GBaud
128
Figure 34: Receiver AC Timing Specifications - 2.5 GBaud
128
Figure 35: Receiver AC Timing Specifications - 3.125 GBaud
129
Figure 36: Single Frequency Sinusodial Jitter Limits
129
Figure 37: Receiver Input Compliance Mask
130
Figure 38: Receiver Input Compliance Mask Parameters Exclusive of Sinusodial Jitter
130
Figure 39: P-Port Signals Connected to a QDRII SRAM
131
Figure 40: Timing Waveform of Combined Read and Write Cycles
133
Figure 41: Diagram of the JTAG Logic
135
Figure 42: State Diagram of the 80KSBR200’s TAP Controller
136
Figure 43: Diagram of Observe-only Input Cell
137
Figure 44: Diagram of Output Cell
137
Figure 45: Diagram of Output Enable Cell
138
Figure 46: Diagram of Bi-directional Cell
138
Figure 47: Implementation of Write during Configuration Register Access
142
Figure 48: Implementation of Read during Configuration Register Access
143
Figure 49: JTAG DC Electrical Specifications (VDD3 = 3.3V)
143
Figure 50: JTAG DC Electrical Specifications (VDD3 = 2.5V)
143
Figure 51: JTAG AC Electrical Specifications
144
Figure 52: JTAG Timing Specifications
144
7 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.