80KSBR200 Datasheet, PDF (157/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
W15
GNDS
Y4
GNDS
Y16
GNDS
AA5
GNDS
AA10
GNDS
AA15
GNDS
AB4
GNDS
A6
ID0
B6
ID1
A7
ID2
B7
ID3
D6
ID4
C8
ID5
D8
ID6
C10
ID7
C11
ID8
C12
ID9
U2
IDS
AA1
IRQ0
SERDES
Ground
(CMOS)
SERDES
Ground
(CMOS)
SERDES
Ground
(CMOS)
SERDES
Ground
(CMOS)
SERDES
Ground
(CMOS)
SERDES
Ground
(CMOS)
SERDES
Ground
(CMOS)
I²C
(VDD, GND) / CMOS Input
I²C
I²C
I²C
I²C
I²C
I²C
I²C
I²C
I²C
ID Select
Interrupt 0
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD3, GND) / CMOS Output
Advanced Datasheet*
Analog GND for TX/RX pairs. All pins must be tied to single
potential ground plane.
Analog GND for TX/RX pairs. All pins must be tied to single
potential ground plane.
Analog GND for TX/RX pairs. All pins must be tied to single
potential ground plane.
Analog GND for TX/RX pairs. All pins must be tied to single
potential ground plane.
Analog GND for TX/RX pairs. All pins must be tied to single
potential ground plane.
Analog GND for TX/RX pairs. All pins must be tied to single
potential ground plane.
Analog GND for TX/RX pairs. All pins must be tied to single
potential ground plane.
I²C Slave ID address bit 0. This should be set statically to Vdd or
GND at power-up. NOTE: SUPPLY / LEVELS REQUIREMENTS
ARE UNQUE FROM THE OTHER I²C PINS.
I²C Slave ID address bit 1. This should be set statically to Vdd or
GND at power-up.
I²C Slave ID address bit 2. This should be set statically to Vdd or
GND at power-up.
I²C Slave ID address bit 3. This should be set statically to Vdd or
GND at power-up.
I²C Slave ID address bit 4. This should be set statically to Vdd or
GND at power-up.
I²C Slave ID address bit 5. This should be set statically to Vdd or
GND at power-up.
I²C Slave ID address bit 6. This should be set statically to Vdd or
GND at power-up.
I²C Slave ID address bit 8. This should be set statically to Vdd or
GND at power-up.
I²C Slave ID address bit 7. This should be set statically to Vdd or
GND at power-up.
I²C Slave ID address bit 9. This should be set statically to Vdd or
GND at power-up.
sRIO 8/16 bit Destination ID Select
This is an interrupt output pin whose value is given by the Error
Management Block.
157 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.