80KSBR200 Datasheet, PDF (1/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

sRIO SERIAL BUFFER
FLOW-CONTROL DEVICE
Advanced Datasheet
80KSBR200
Device Overview
The IDT80KSBR200 is a high speed Serial Buffer (SerB) that can
connect to any Serial RapidIO compliant interface. This device is built to
work with any sRIO device and especially with the IDT Pre-Processing
Switch (PPS), IDT70K200. The SerB performs buffering and off-loading
of data as well as buffer-delay of data samples in various environments.
This device primarily acts as an master in which the SerB bursts data to
a programmed memory location once some criteria have been meet.
This combination of storage and flexibility make it the perfect buffering
solution for sRIO systems.
Features
◆ _{Serial RapidIO Port}
◆ _{Interface - sRIO}
– One four-lane (4x) link, configurable to one-lane (1x) link
– Port Speeds selectable: 3.125 Gbps, 2.5 Gbps, or 1.25 Gbps
– Short haul or long haul reach for each PHY speed
– Support 8-bit and 16-bit deviceID
– Error management supports standard
– sRIO version 1.3
– Class 1+ End Point Device
◆ _{10 Gbps Throughput}
◆ _{18Mbit Internal Density}
Block Diagram
S-Port 1
◆ _{Programmable Target Address}
◆ _{Packet Tally Indicator}
◆ _{Packet Interval Timer}
◆ _{Replace Missing Packet}
◆ _{Optional External QDR SRAM Available}
– Up to 72Mbit external QDR SRAM
– QDR SRAM, 200 MHz; (18M, 36M, 72M)
◆ _{Seamless Integration of Internal and External Memory}
– Internal and external memory functions as a single buffer
◆ _{Single Port Buffering}
◆ _{Status Flags for Combined Internal/External Memories}
– Full, Empty, Partially Empty, Partially Full
◆ _{Direct or polled operation of flag status bus}
◆ _{Optional Watermark}
– Serial Buffer can Either Send a Flag or Transmit Data at a Specific Packet
Count
◆ _{Interface - I}2_{C Interface Port}
– One I²C port for maintenance and error reporting
◆ _{Interface - JTAG Interface}
– JTAG Functionality for boundary scan and programming
◆ _{High-Speed CMOS Technology}
– 1.2V Core operation with 3.3/2.5V JTAG interface
◆ _{Package: 484-pin Plastic Ball Grid Array}
– 23mm x 23mm, 1.0mm ball pitch
1x/4x sRIO
Interface
Queue 0
18 Mbits
TCK
TMS
TDI
TDO
SCL
SDA
MR
FR
Configuration
and
Flag Registers
Flags
82
Hardwire
Config
2
2
K/K CQ
CQ ^D
2
PHY Clk
QDR Clk
P-Port
drw01 DSC-6730
A Rd Wr
Q
1 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.