80KSBR200 Datasheet, PDF (87/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
Port 0 Error Rate CSR
The Port 0 Error Rate register is a 32-bit register used with the Port 0 Error Rate Threshold register to monitor and
control the reporting of transmission errors.
Name: P0_ERR_RATE_CSR
Address: 0x000668
Bit
7:0
Field Name
Reset
Value
ERR_RATE_CNTR 0x00
Comment
Error Rate Counter:
These bits maintain a count of the number of transmission errors that
have been detected by the port, decremented by the Error Rate Bias
mechanism, to create an indication of the link error rate.
15:8
PEAK_ERR_RATE 0x00
17:16 ERR_RATE_REC 2b00
Software should not attempt to write this field to a value higher than
failed threshold trigger plus the number of errors specified in the
ERR field (the maximum ERC value).
Peak Error Rate:
This field contains the peak value attained by the error rate counter.
Error Rate Recovery:
These bits limit the incrementing of the error rate counter above the
failed threshold trigger:
2b00 - only count 2 errors above
2b01 - only count 4 errors above
2b10 - only count 16 errors above
2b11 - do not limit incrementing the error rate count
23:18
31:24
-
ERR_RATE_BIAS
0
0x80
Note that the Error Rate Counter will never increment above 0cFF,
even if the combination of the settings of ERR and the failed thresh-
old trigger might imply that it would.
Reserved.
Error Rate Bias:
These bits provide the error rate bias value:
0x00 - do not decrement the error rate counter
0x01 - decrement every 1ms (+/-34%)
0x02 - decrement every 10ms (+/-34%)
0x04 - decrement every 100ms (+/-34%)
0x08 - decrement every 1s (+/-34%)
0x10 - decrement every 10s (+/-34%)
0x20 - decrement every 100s (+/-34%)
0x40 - decrement every 1000s (+/-34%)
0x80 - decrement every 10000s (+/-34%)
Note:
1.
Other values are reserved and will cause undefined operation.
Table 49 Port 0 Error Rate CSR
The above register is described in the RIO Specification Part 8, sec. 2.3.2.17
Port 0 Error Rate Threshold CSR
The Port 0 Error Rate Threshold register is a 32-bit register used to control the reporting of the link status to the system
host.
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.