80KSBR200 Datasheet, PDF (165/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
U6
VDD
U8
VDD
U10
VDD
U12
VDD
U14
VDD
A2
VDD3
B1
VDD3
C2
VDD3
F3
G2
H3
M3
N2
P3
Y6
Y8
Y12
Y14
AA7
AA13
A21
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDQ
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
2.5V / 3.3V
JTAG Power
(CMOS)
2.5V / 3.3V
JTAG Power
(CMOS)
2.5V / 3.3V
JTAG Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
1.5V Digital
Power (CMOS)
Advanced Datasheet*
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital JTAG Pin VDD3. All pins must be tied to single potential
power supply plane.
Digital JTAG Pin VDD3. All pins must be tied to single potential
power supply plane.
Digital JTAG Pin VDD3. All pins must be tied to single potential
power supply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
165 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.