80KSBR200 Datasheet, PDF (161/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
AB6
AA6
W6
W7
AB14
AA14
W14
W13
AB9
AB8
W9
Y9
AB11
AB12
W11
Y11
B12
S2_RXN0
S2_RXP0
S2_RXN1
S2_RXP1
S2_RXN2
S2_RXP2
S2_RXN3
S2_RXP3
S2_TXN0
S2_TXP0
S2_TXN1
S2_TXP1
S2_TXN2
S2_TXP2
S2_TXN3
S2_TXP3
SCEN
Port 2 Receive (VDDS, GNDS)
Port 2 Receive (VDDS, GNDS)
Port 2 Receive (VDDS, GNDS)
Port 2 Receive (VDDS, GNDS)
Port 2 Receive (VDDS, GNDS)
Port 2 Receive (VDDS, GNDS)
Port 2 Receive (VDDS, GNDS)
Port 2 Receive (VDDS, GNDS)
Port 2 Transmit (VDDS, GNDS)
Port 2 Transmit (VDDS, GNDS)
Port 2 Transmit (VDDS, GNDS)
Port 2 Transmit (VDDS, GNDS)
Port 2 Transmit (VDDS, GNDS)
Port 2 Transmit (VDDS, GNDS)
Port 2 Transmit (VDDS, GNDS)
Port 2 Transmit (VDDS, GNDS)
SCAN
(VDD, GND) / CMOS Input
C4
SCL
I²C
C5
SDA
I²C
(VDD3, GND) / CMOS Input
(VDD3, GND) / CMOS IO
W3
SP1S0
S-Port 1 Speed (VDD, GND) / CMOS Input
Select
Y3
SP1S1
S-Port 1 Speed (VDD, GND) / CMOS Input
Select
AA2
STOA
SERDES
Analog
Y2
STOD
SERDES
Digital
B4
TCK
JTAG
(VDD3, GND) / CMOS Input
B5
TDI
JTAG
(VDD3, GND) / CMOS Input
A5
TDO
JTAG
(VDD3, GND) / CMOS Output
Advanced Datasheet*
Negative end of differential receiver, S-Port 2, Lane 0
Positive end of differential receiver, S-Port 2, Lane 0
Negative end of differential receiver, S-Port 2, Lane 1
Positive end of differential receiver, S-Port 2, Lane 1
Negative end of differential receiver, S-Port 2, Lane 2
Positive end of differential receiver, S-Port 2, Lane 2
Negative end of differential receiver, S-Port 2, Lane 3
Positive end of differential receiver, S-Port 2, Lane 3
Negative end of differential transmitter, S-Port 2, Lane 0
Positive end of differential transmitter, S-Port 2, Lane 0
Negative end of differential transmitter, S-Port 2, Lane 1
Positive end of differential transmitter, S-Port 2, Lane 1
Negative end of differential transmitter, S-Port 2, Lane 2
Positive end of differential transmitter, S-Port 2, Lane 2
Negative end of differential transmitter, S-Port 2, Lane 3
Positive end of differential transmitter, S-Port 2, Lane 3
SCAN Enable. SCAN is enabled when SCEN = 1. Scan clock is
provided by SCK while SCEN = 1. Internal pull-down ensures dis-
able if this pin is not driven.
I²C Clock. This is also repurposed for the SCAN clock when
SCEN = 1.
I²C Serial Data IO. Data direction is determined by the I²C Read/
Write bit. See I²C functionality for further detail.
Speed Select Pins. These pins define S-Port port speed at
RESET for all ports. The RESET setting may be overridden by
subsequent programming of the QUAD_CTRL register.
SP1S[1:0] = {00 = 1.25G, 01 = 2.5G, 10 = 3.125G, 11 =
RESERVED}. These pins must remain STATICALLY BIASED
after power-up.
Speed Select Pins. These pins define S-Port port speed at
RESET for all ports.
SERDES Analog Test Output. Used for observing SERDES out-
puts.
SERDES Digital Test Output. Used for observing SERDES out-
puts.
JTAG Tap Port Clock
JTAG Tap Port Input
JTAG Tap Port Output
161 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.