80KSBR200 Datasheet, PDF (102/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Name: SP_PKT_XMT_CNT
Address: 0x1860C
Advanced Datasheet*
Bit
Field Name
Type
Reset
Value
Comment
31:0 SPKT_XMT_CNT RW
32h0
S-Port Packet Transmitted Counter:
Reset 0 by reading
Table 83 S-Port Packet Transmitted Counter
8.4 SERDES Quad Control Register
The sRIO specification has defined registers for use in configuring and controlling the 1x/4x Quad Serdes sRIO port (S-
Port 1 on the SerB). The SerB shall utilize the standard register and observe standard 1x/4x configuration protocols.
For the rest of the serial ports definition, refer to “RapidIO Interconnect Specification Part VI: Physical Layer 1x/4x LP-
Serial Specification.
Name: SERDES_QUAD_CTRL Address: 0x18C30
Bit
Field Name
1:0
-
4:2
TCOEFF[2:0]
6:5
-
9:7
TXDRVSEL
31:10 -
Type
Reset
Value
Comment
0
Reserved
RW
3b0
0
Transmit pre-emphasis control:
000 = 0% emphasis
001 = 6.5% emphasis
010 = 13% emphasis
011 = 19.5% emphasis
100 = 26% emphasis
101 = 32.5% emphasis
110 = 39% emphasis
111 = 45.5% emphasis
Reserved
RW
3b010 Tx drive strength select
000 = maximum drive strength
010 = sRIO long haul
100 = sRIO short haul
111 = minimum drive strength
0
Reserved
Table 84 SERDES Quad Control Register
8.5 Flag and Flag Mask Registers
The flag registers are 32-bit registers and include an additional 32-bit register for the flag masks. Each register contains
a maximum of 8 flags plus the masks and destination IDs associated with those flags. The typical flag register content is
shown below table. The flags within a register are selected to generate same interrupt or generate doorbells destined for
the same location. The interrupting flag may individually be identified by the register contents that may be read or sent with
a doorbell.
Contained within each flag register is a series of four mask registers for the flags. The flag mask registers are used to
create doorbells and interrupts. This means there are five register locations associated with each flag.
The content of each flag register is available for reading at any time by any of the following methods:
◆ _{sRIO commands}
◆ _I2_{C Interface}
◆ _JTAG
102 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.